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ISL5640EVAL の電気的特性と機能

ISL5640EVALのメーカーはIntersil Corporationです、この部品の機能は「3V Dual 8-Bit/ 20/40/60MSPS A/D Converter with Internal Voltage Reference」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL5640EVAL
部品説明 3V Dual 8-Bit/ 20/40/60MSPS A/D Converter with Internal Voltage Reference
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL5640EVAL Datasheet, ISL5640EVAL PDF,ピン配置, 機能
ADVANCE INFORMATION Data Sheet
ISL5640
June 2000 File Number 4657.3
3V Dual 8-Bit, 20/40/60MSPS A/D
Converter with Internal Voltage Reference
The ISL5640 is a monolithic, dual 8-bit analog-to-digital
converter fabricated in an advanced CMOS process. It is
designed for high speed applications where integration,
bandwidth and accuracy are essential. The ISL5640
features a 9-stage pipeline architecture. The fully pipelined
architecture and an innovative input stage enable the
ISL5640 to accept a variety of input configurations, single-
ended or fully differential. Only one external clock is
necessary to drive both converters and an internal band-gap
voltage reference is provided. This allows the system
designer to realize an increased level of system integration
resulting in decreased cost and power dissipation.
The ISL5640 has excellent dynamic performance while
consuming less than 100mW power at 40MSPS. The A/D
only requires a single +3.0V power supply. Data output
latches are provided which present valid data to the output
bus with a latency of 5 clock cycles.
The ISL5640 is offered in 20MSPS, 30MSPS, 40MSPS and
60MSPS sampling rates.
Ordering Information
PART
NUMBER
ISL5640/2IN
TEMP.
RANGE
(oC)
PACKAGE
SAMPLING
RATE
PKG. NO. (MSPS)
-40 to 85 48 Ld LQFP Q48.7x7
20
ISL5640/3IN -40 to 85 48 Ld LQFP Q48.7x7
ISL5640/4IN -40 to 85 48 Ld LQFP Q48.7x7
ISL5640/6IN -40 to 85 48 Ld LQFP Q48.7x7
ISL5640 EVAL 25 Evaluation Platform
30
40
60
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .40MSPS
• 7.4 Bits at fIN = 1MHz
• Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 100mW
• Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . <1mW
• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz
• SFDR at fIN = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . .55dB
• Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB
• On-Chip Sample and Hold Amplifiers
• Internal Bandgap Voltage Reference . . . . . . . . . . . . 1.25V
• Single Supply Voltage Operation . . . . . . . . . . . . . . . +3.0V
• Offset Binary or Two’s Complement Output Format
• Dual 8-Bit A/D Converters on a Monolithic Chip
• Pin Compatible Upgrade to AD9288
Applications
• Wireless Local Loop
• PSK and QAM I&Q Demodulators
• Medical Imaging
• High Speed Data Acquisition
Pinout
48 LEAD LQFP
TOP VIEW
GND
IIN+
IIN-
DFS
IVRIN
VROUT
QVRIN
S1
S2
QIN-
QIN+
GND
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
N/C
N/C
GND
DVCC
GND
AVCC
AVCC
GND
DVCC
GND
N/C
N/C
3-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000

1 Page





ISL5640EVAL pdf, ピン配列
Typical Application Schematic
ISL5640
ISL5640
IIN +
(2) IIN+
(LSB) ID0 (37)
ID0
ID1 (38)
ID1
IIN- (3) IIN-
ID2 (39)
ID3 (40)
ID2
ID3
ID4 (31)
ID4
ID5 (42)
ID5
ID6 (43)
ID6
(MSB) ID7 (44)
ID7
QIN +
QIN -
0.1µF
+3V +
10µF
0.1µF
(11) QIN+
(10) QIN-
(5) IVRIN
(6) QVRIN
(7) VROUT
(LSB) QD0 (24)
QD1 (23)
QD2 (22)
QD3 (21)
QD4 (20)
QD5 (19)
QD6 (18)
(MSB) QD7 (17)
QD0
QD1
QD2
QD3
QD4
QD5
QD6
QD7
ICLK (47)
QCLK (14)
CLOCK
S1 (8)
S2 (9)
DFS (4)
(13,30,31,48) AVCC DVCC (15, 28, 33, 46)
S1
S2
DFS
0.1µF
+ 3V
10µF
(12,29,32) AGND DGND (16, 27, 34, 45)
BNC AGND DGND
10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
3-3


3Pages


ISL5640EVAL 電子部品, 半導体
ISL5640
Electrical Specifications
AVDD = DVDD
CL = 10pF; TA
=
=
2+53o.3CV; ;UVnIlNes=s1O.5th0eVr;wfSise=
40MSPS
Specified
at 50% Duty Cycle;
(Continued)
PARAMETER
TEST CONDITIONS
MIN
Analog Input Bias Current, IBA or IBB
VINA/VINB = ART/BRT, ARB/BRB, DC
(Notes 2, 3)
-
Full Power Input Bandwidth, FPBW
REFERENCE VOLTAGE INPUT
fS = 40MHz, (Note 2)
-
Reference Voltage Input Range
-
Total Reference Resistance, RRIN
Reference Current, IRIN
SAMPLING CLOCK INPUT
-
-
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Input Logic High Current, IIH
Input Logic Low Current, IIL
Input Capacitance, CIN
DIGITAL OUTPUTS
CLK
CLK
CLK, VIH = 3.3V
CLK, VIL = 0V
CLK
2.0
-
-
-
-
Output Logic High Voltage, VOH
Output Logic Low Voltage, VOL
Output Logic High Voltage, VOH
Output Logic Low Voltage, VOL
Output Capacitance, COUT
TIMING CHARACTERISTICS
IOH = 100µA; DVDD = 3.3V
IOL = 1.5mA; DVDD = 3.3V
IOH = 100µA; DVDD = 3.0V
IOL = 100µA; DVDD = 3.0V
-
-
-
-
-
Aperture Delay, tAP
Aperture Jitter, tAJ
Data Output Hold, tH
Data Output Delay, tOD
Data Latency, tLAT
Power-Up Initialization
For a Valid Sample (Note 2)
Data Invalid Time (Note 2)
-
-
-
-
-
-
Sample Clock Pulse Width (Low)
(Note 2)
11.25
Sample Clock Pulse Width (High)
(Note 2)
11.25
Sample Clock Duty Cycle Variation
-
POWER SUPPLY CHARACTERISTICS
Analog Supply Voltage, AVDD
Digital Supply Voltage, DVDD
Supply Current, IDD
Power Dissipation
(Note 2)
(Note 2)
fS = 40MSPS
3.0
3.0
-
-
Offset Error Sensitivity, VOS
A VDD or DVDD = 3.3V ±5%
Gain Error Sensitivity, FSE
A VDD or DVDD = 3.3V ±5%
NOTES:
1. Parameter guaranteed by design or characterization and not production tested.
2. With the clock low and DC input.
-
-
TYP
-
250
-
300
-
-
-
-
-
-
-
-
-
-
-
4
5
10.7
11.7
5
-
12.5
12.5
±5
3.3
3.3
30.3
100
±0.125
±0.15
MAX
-
-
-
-
-
-
0.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.6
3.6
-
110
-
-
UNITS
µA
MHz
V
mA
V
V
µA
µA
pF
V
V
V
V
pF
ns
psRMS
ns
ns
Cycles
Cycles
ns
ns
%
V
V
mA
mW
LSB
LSB
3-6

6 Page



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部品番号部品説明メーカ
ISL5640EVAL

3V Dual 8-Bit/ 20/40/60MSPS A/D Converter with Internal Voltage Reference

Intersil Corporation
Intersil Corporation


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