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PDF ISL5586 Data sheet ( Hoja de datos )
| Número de pieza | ISL5586 | |
| Descripción | Low Power Ringing SLIC for Home Gateways | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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TM
Data Sheet
ISL5586
June 2001
File Number 4924.1
Low Power Ringing SLIC for Home
Gateways
The ISL5586 is a very low
power Ringing Subscriber
Interface circuit designed for
use with the Broadcom*
BCM3352 Cable Modem
Chip, with on-board voiceband codecs, or other 3.3V
voiceband codec devices.
The ISL5586 provides on board ringing signal generation up
to 95V peak supporting sinusoidal or trapezoidal
waveshapes with DC offset. Loop start and ground start
trunks are supported, and an open circuit DC voltage of less
than 56V is maintained on the subscriber loop in the on-hook
condition, in compliance with MTU operation and the safety
requirements of UL-1950.
Together with the Broadcom BCM3352, the ISL5586
provides resistive and complex two wire impedance
matching and transhybrid balancing. Also supported are on-
hook transmission of caller id signals, soft and hard polarity
reversal and 12/16kHz subscriber pulse metering systems
used in Europe and Asia, thereby allowing a low cost, low
risk, global product design to be achieved.
Related Literature
• Evaluation Board for the ISL5586 family AN9918
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Block Diagram
POL CDCP CDCM
VBL VBH
ILIM
DC
CONTROL
BATTERY
SWITCH
TIP
RING
TL
2-WIRE
PORT
TRANSIENT
CURRENT
LIMIT
TRANSMIT
SENSING
INTERNAL
LOOP BACK
DETECTOR
LOGIC
RTD RD
*Broadcom is a registered trademark of Broadcom Corp.
DET
Features
• Interfaces to Broadcom 3352 cable modem device
• Very low on-hook power consumption
- 64mW @ Vbh = 75V
• User Programmable constant current to the subscriber
loop
• On Chip ring generation
- Balanced to 95 Vpk
• Sinewave, Trapezoid, DC offset
• Programmable loop start and ring trip detectors
• Loop start, Ground Start, Polarity Reversal (soft/hard)
• On-Hook transmission and pulse metering support
• Integrated battery switch
• Open circuit line voltage clamp
• Compatible with 3.3V devices
• TR-57 compliant Longitudinal balance
• 28 PLCC packaging
• Latch-up free Bipolar design
• Thermal protection
Applications
• Cable Modems
• Voice Over DSL (VoDSL)
• Broadband Wireless Access
• Voice Over Internet Protocol (VoIP)
• ISDN Terminal Adapters (TA)
• Small Office Home Office PBX
• Wireless Local Loop
RINGING
PORT
4-WIRE
PORT
CONTROL
LOGIC
BSEL
VRSP
VRSM
VRXP
VRXM
-IN
VZO
VFB
VTXP
VTXM
F2
F1
F0
4-1
RSLIC18™ is a trademark of Intersil Corporation.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
1 page  
ISL5586
Electrical Specifications
Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V,
AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600Ω,
2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection
resistors = 0Ω. These parameters apply generically to each product offering. (Continued)
PARAMETER
Forward Active, BSEL = 2.0V, VBH = -100V
Forward Active, BSEL = 2.0V, VBH = -85V
Forward Active, BSEL = 2.0V, VBH = -75V
Ringing, BSEL = 2.0V, VBH = -100V
Ringing, BSEL = 2.0V, VBH = -85V
Ringing, BSEL = 2.0V, VBH = -75V
Forward Loopback, BSEL = 0.8V, VBL = -24V
Tip Open, BSEL = 2.0V
Power Denial, BSEL = 0.8V or 2.0V
ON HOOK POWER DISSIPATION (Note 6)
Forward or Reverse
Low Power Standby
Ringing
OFF HOOK POWER DISSIPATION (Note 6)
Forward or Reverse
POWER SUPPLY REJECTION RATIO
VCC to 2-Wire, BSEL = 0.8V
VCC to 4-Wire, BSEL = 0.8V
VBL to 2-Wire, BSEL = 0.8V
VBL to 4-Wire, BSEL = 0.8V
VBH to 2-Wire, BSEL = 2.0V
TEST CONDITIONS
ICC
IBL
IBH
ICC
IBL
IBH
ICC
IBL
IBH
ICC
IBL
IBH
ICC
IBL
IBH
ICC
IBL
IBH
ICC
IBL
ICC
IBL
ICC
IBL
VBL = -24V
VBH = -100V
VBH = -85V
VBH = -75V
VBH = -100V
VBH = -85V
VBH = -75V
VBL = -24V, ILIM = 25mA, RL = 300Ω
f = 50kHz
f = 300Hz ≤ f ≤ 3400Hz
f = 8kHz ≤ f ≤ 16kHz
f = 50Hz
f = 300Hz ≤ f ≤ 3400Hz
f = 8kHz ≤ f ≤ 16kHz
f = 50Hz
f = 300Hz ≤ f ≤ 3400Hz
f = 8kHz ≤ f ≤ 16kHz
f = 50Hz
f = 300Hz ≤ f ≤ 3400Hz
f = 8kHz ≤ f ≤ 16kHz
f = 50Hz
f = 300Hz ≤ f ≤ 3400Hz
f = 8kHz ≤ f ≤ 16kHz
MIN TYP MAX
- 7.0 9.0
- 1.4 2.0
- 1.8 3.0
- 6.6 8.5
- 1.35 2.0
- 1.60 2.75
- 6.3 8.0
- 1.25 2.0
- 1.45 2.5
- 7.4 10.0
- 1.5 2.0
- 2.2 3.0
- 6.80 9.25
- 1.36 2.0
- 2.1 3.0
- 6.4 8.5
- 1.26 2.0
- 2.0 3.0
- 10.3 13.5
- 23.0 32.0
- 3.2 -
- 0.1 -
- 3.4 6.0
- 0.22 0.50
- 57 -
- 83 -
- 70 -
- 64 -
- 294 -
- 236 -
- 206 -
- 305 -
- 50 -
- 45 -
- 28 -
- 70 -
- 55 -
- 40 -
- 25 -
- 38 -
- 28 -
- 27 -
- 36 -
- 23 -
- 27 -
- 35 -
- 23 -
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
mW
mW
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
4-5
5 Page 
ISL5586
I1
POL
75kΩ
CPOL
I2
FIGURE 7. REVERSAL TIMING CONTROL
Power Dissipation
The power dissipation equations for forward active operation
also apply to the reverse active mode.
Ringing
Overview
The Ringing mode (RNG, 100) provides linear amplification
to support a variety of ringing waveforms. A programmable
ring trip function provides loop supervision and auto
disconnect upon ring trip. The device is designed to operate
from the high battery during this mode.
Architecture
The SLIC provides linear amplification to the differential
signal applied to the ringing inputs (VRSP, VRSM). The
differential ringing gain of the device is 100V/V. The circuit
model for the ringing path is shown in Figure 8.
R
20
TIP
-
+
RING 20
+-
R
R/8
+- VBH
2
5:1
1.25R
R
1.25R
R
VRSP
VRSM
FIGURE 8. LINEAR RINGING MODEL
The voltage gain from the differential ringing input to the Tip
output is 50V/V. The resistor ratios provide a gain of 10 and
the current mirror provides a gain of 5. The voltage gain from
the differential input to the Ring output is -50V/V. The
equations for the Tip and Ring outputs during ringing are
provided below.
VT= -V----B2----H-- + (50 × VDIF )
(EQ. 29)
4-11
VR= -V----B2---H---–(50 × VDIF)
(EQ. 30)
When the differential input signal is zero, the Tip and Ring
amplifier outputs are centered at half battery. The device
provides auto centering for easy implementation of
sinusoidal ringing waveforms. Both AC and DC control of the
Tip and Ring outputs is available during ringing. This feature
allows for DC offsets as part of the ringing waveform.
Ringing Input Terminals
The differential terminals feature high input impedance
which allows the use of low value capacitors for AC coupling
the ring signal if necessary. The Ringing input is enabled
only during the ringing mode, therefore a free running
oscillator may be connected at all times.
When operating from a battery of -100V, each amplifier, Tip
and Ring, will swing a maximum of 95VP-P. Hence, the
maximum differential signal swing between VRSP and VRSM
to achieve full scale ringing is approximately 1.9VP-P.
Logic Control
Ringing patterns consist of silent and ringing intervals. The
ringing to silent pattern is called the ringing cadence. During
the silent portion of ringing, the device can be programmed
to any other operating mode. The most likely candidates are
low power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full-wave rectifies the
ringing current, which is then filtered with external components
RRT and CRT. The resistor RRT sets the trip threshold and the
capacitor CRT sets the trip response time. Most applications will
require a trip response time less than 150ms.
Three very distinct actions occur when the device detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the Ringing inputs are
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.
Power Dissipation
The power dissipation during ringing is dictated mostly by the
load driving requirements and the ringing waveform. The key to
valid power calculations is the correct definition of average and
RMS currents. The average current defines the high battery
supply current. The RMS current defines the load current.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, Pr, and the silent interval power, Ps.
PRNG= Pr × -t-r----+t--r--t--s- + Ps × -t--r---t+-s----t--s-
(EQ. 31)
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL5586.PDF ] | |
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