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ISL5239EVAL1 の電気的特性と機能

ISL5239EVAL1のメーカーはIntersil Corporationです、この部品の機能は「Pre-Distortion Linearizer」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL5239EVAL1
部品説明 Pre-Distortion Linearizer
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL5239EVAL1 Datasheet, ISL5239EVAL1 PDF,ピン配置, 機能
®
Data Sheet
July 2002
ISL5239
FN8039.1
Pre-Distortion Linearizer
The ISL5239 Pre-Distortion Linearizer
(PDL) is a full featured component for
Power Amplifier (PA) linearization to
improve PA power efficiency and reduce PA cost.
The Radio Frequency (RF) PA is one of the most expensive and
power-consuming devices in any wireless communication
system. The ideal RF PA would have an entirely linear
relationship between input and output, expressed as a simple
gain which applies at all power levels. Unfortunately, realizable
RF amplifiers are not completely linear and the use of pre-
distortion techniques allows the substitution of lower cost/power
PA’s for higher cost/power PA’s.
The ISL5239 pre-distortion linearizer enables the linearization of
less expensive PA’s to provide more efficient operation closer to
saturation. This provides the benefit of improved linearity and
efficiency, while reducing PA cost and operational expense.
The ISL5239 features a 125MHz pre-distortion bandwidth
capable of full 5th order intermodulation correction for signal
bandwidths up to 20MHz. This bandwidth is particularly well
suited for 3G cellular deployments of UMTS and CDMA2000.
The device also corrects for PA memory effects that limit pre-
distortion performance including self heating.
The ISL5239 combines an input formatter and interpolator, pre-
distortion linearizer, an IF converter, correction filter,
gain/phase/offset adjustment, output formatter, and input and
feedback capture memories into a single chip controlled by a 16-
bit linearizer interface.
The ISL5239 supports log of power, linear magnitude, and linear
power based pre-distortion, utilizing two Look-Up Table (LUT)
based algorithms for the pre-distortion correction. The device
provides programmable scaling and offset correction, and
provides for phase imbalance adjustment.
Block Diagram
Features
• Output Sample Rates Up to 125MSPS
• Full 20MHz Signal Bandwidth
• Dynamic Memory Effects Compensation
• Input and Feedback Capture Memories
• LUT-based Digital Pre-distortion
• Two 18-bit Output Busses with Programmable Bit-Width
• 16-Bit Parallel µProcessor Interface
• Input Interpolator x2, x4, x8
• Programmable Frequency Response Correction
• Low Power Architecture
• Threshold Comparator for Internal Triggering
• Quadrature or Digital IF Architecture
• Lowest-Cost Full-Featured Part Available
Applications
• Base Station Power Amplifier Linearization
• Operates with ISL5217 in Software Radio Solutions
• Compatible with the ISL5961 or ISL5929 D/A Converters
Ordering Information
PART
NUMBER
ISL5239KI
ISL5239EVAL1
TEMP
RANGE (oC) PACKAGE
-40 to 85 196 Ld BGA
25 Evaluation Kit
PKG. DWG. #
V196.15x15
CLK
TRIGIN
IIN<17:0>
QIN<17:0>
CLKOUT
ISTRB
TRIGOUT
A<5:0>
P<15:0>
CS
WR
RD
BUSY
RESET
INPUT
FORMATTER
AND
INTERPOLATOR
X1, X2, X4, X8
uP INTERFACE
PRE-DISTORTER
WITH
TWO 1K x 60
LUTs
INPUT
MEMORY
(2k x 32)
IF CONVERTER
REAL 1X
REAL 2X
COMPLEX
CORRECTION
FILTER
REAL 1X
REAL 2X
COMPLEX
GAIN /
PHASE
OFFSET
ADJUST
OUTPUT
DATA
FORMATTER
8-18 BIT-WIDTH
SERCLK
SERSYNC
SEROUT
SERIN
IOUT<17:0>
QOUT<17:0>
FEEDBACK
MEMORY
(1k x 20)
FBCLK
FB<19:0>
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
CommLink™ is a trademark of Intersil Americas Inc.

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ISL5239EVAL1 pdf, ピン配列
ISL5239
Pinout
196 CABGA
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
NC VCCC IIN16 IIN12 IIN9 IIN4 IIN0 QOUT15 GND QOUT11 GND VCCIO VCCC NC
B
ISTRB NC IIN17 IIN14 VCCC IIN7 IIN3 VCCIO VCCIO QOUT9 QOUT6 QOUT4 NC GND
C
A3 A0 A2 IIN15 IIN11 IIN8 IIN2 QOUT16 QOUT12 VCCC QOUT7 QOUT1 QOUT3 QOUT0
D
CS A1 A5 IIN13 IIN10 IIN6 IIN1 QOUT17 QOUT13 QOUT8 QOUT2 VCCIO QOUT5 FB17
E
P0 VCCC RD
A4 WR
IIN5 GND VCCC QOUT14 QOUT10 FB14 FB19 FB18 VCCC
F
VCCIO P1 P2 P3 P4
FB13 FB16 FB15 GND FB10
G
P7 P6 P5 GND P11
SEROUT FB9 FB12 FB11 SERIN
H
P10 P12 VCCIO P8
P9
SERSYNC GND VCCIO SERCLK CLKOUT
J
CLK GND RESET P14 P15
TRIGOUT FB7 FB6 FB5 FB8
K
P13 TDO TCK BUSY QIN6 QIN0 VCCC GND IOUT11 GND FB0 VCCC FB3 FB4
L
DCTEST TDI
TMS QIN17 QIN9 QIN2 VCCIO IOUT13 IOUT9 VCCC IOUT4 FB1 TRIGIN FB2
M
QIN16 QIN15 QIN13 QIN11 QIN7 QIN4 IOUT16 GND IOUT7 VCCIO IOUT3 IOUT0 IOUT2 FBCLK
N
TRST NC QIN14 QIN10 VCCC QIN3 IOUT17 IIOUT12 IOUT10 IOUT8 GND VCCIO NC IOUT1
P
NC VCCC QIN12 QIN8 QIN5 QIN1 IOUT15 IOUT14 VCCIO GND IOUT6 IOUT5 VCCC NC
POWER PIN
GROUND PIN
SIGNAL PIN
THERMAL BALL
NC (Do not connect)
Pin Descriptions
NAME
TYPE
DESCRIPTION
POWER SUPPLY
VCCC
- Positive Device Core Power Supply Voltage, 1.8V ±0.18V.
VCCIO
- Positive Device Input/Output Power Supply Voltage, 3.3V ±0.165V.
GND
- Common Ground, 0V
MICROPROCESSOR INTERFACE AND CONTROL
CLK I Input Clock. Rising edge drives all of the devices synchronous operations, except feedback capture.
RESET
I Reset. (Active Low). Asserting reset will clear all configuration registers to their default values, reset all internal
states, and halt all processing.
P<15:0>
I/O 16-bit bi-directional data bus that operates with A<5:0>, CS, RD, and WR to write to and read from the devices
internal control registers. When the host system asserts CS and RD simultaneously, P<15:0> is an output bus,
under all other conditions, it is an input bus. Bit 15 is the MSB.
3


3Pages


ISL5239EVAL1 電子部品, 半導体
ISL5239
HALFBAND FILTER 2 RESPONSE
0
-20
-40
-60
-80
-100
-120
-140
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
NORMALIZED FREQUENCY (NYQUIST=1)
1
FIGURE 3A. X4, HB1 AND HB2 ENABLED FREQUENCY
RESPONSE
HALFBAND FILTER 3 RESPONSE
0
-20
-40
-60
-80
-100
-120
-140
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
NORMALIZED FREQUENCY (NYQUIST=1)
1
FIGURE 3B. X8, HB1-HB3 ENABLED FREQUENCY RESPONSE
Pre-Distorter (PD)
The function of the Pre-distorter is to compute the
magnitude of the input signal, look up a complex distortion
vector based on the magnitude, and apply that distortion to
the input signal.
The signal magnitude may be computed by any of three
different methods: log of power, linear magnitude or linear
power. The result is scaled and offset by programmable
amounts and becomes the address into a Look-up Table
(LUT).
Two LUTs are available, one of which is ‘live’ in the circuit
and the other is offline and can be loaded via the processor
interface. This configuration allows instantaneous switching
of pre-distortion characteristics without unpredictable
effects on the processed signal.
The LUTs contain a complex distortion vector, as well as
complex delta values which interact with an external
Thermal/Memory calculation circuit to predict the effects of
temperature changes on the RF amplifier’s behavior and
compensate. The average power into the amplifier is
computed and transmitted serially off chip. The external
circuits compute one or two memory effect coefficients
which are combined with the complex delta values in the
LUT to derive the final distortion vector. The distortion
vector is a rectangular complex value which is multiplied
with the input signal resulting in a magnitude based non-
linearity. Access to the LUT is optimized by the use of an
auto incrementing address register which allows the tables
to be updated with only one address register write
operation. Control words 0x10 through 0x1d apply to the
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部品番号部品説明メーカ
ISL5239EVAL1

Pre-Distortion Linearizer

Intersil Corporation
Intersil Corporation


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