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ISL5217 の電気的特性と機能

ISL5217のメーカーはIntersil Corporationです、この部品の機能は「Quad Programmable Up Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL5217
部品説明 Quad Programmable Up Converter
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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ISL5217 Datasheet, ISL5217 PDF,ピン配置, 機能
®
Data Sheet
March 2003
ISL5217
FN6004.2
Quad Programmable Up Converter
The ISL5217 Quad Programmable
UpConverter (QPUC) is a QASK/FM
modulator/FDM upconverter designed
for high dynamic range applications such as cellular
basestations. The QPUC combines shaping and interpolation
filters, a complex modulator, and timing and carrier NCOs into a
single package. Each QPUC can create four FDM channels.
Multiple QPUCs can be cascaded digitally to provide for up to 16
FDM channels in multi-channel applications.
The ISL5217 supports both vector and FM modulation. In vector
modulation mode, the QPUC accepts 16-bit I and Q samples to
generate virtually any quadrature AM or PM modulation format.
The QPUC also has two FM modulation modes. In the FM with
pulse shaping mode, the 16-bit frequency samples are pulse
shaped/bandlimited prior to FM modulation. No band limiting filter
follows the FM modulator. This FM mode is useful for GMSK type
modulation formats. In the FM with band limiting filter mode, the
16-bit frequency samples directly drive the FM modulator. The
FM modulator output is filtered to limit the spectral occupancy.
This FM mode is useful for analog FM or FSK modulation
formats.
The QPUC includes an NCO driven interpolation filter, which
allows the input and output sample rate to have an integer
and/or variable relationship. This re-sampling feature
simplifies cascading modulators with sample rates that do not
have harmonic or integer frequency relationships.
The QPUC offers digital output spectral purity that exceeds
100dB at the maximum output sample rate of 104MSPS, for
input sample rates as high as 6.5MSPS.
A 16-bit microprocessor compatible interface is used to load
configuration and baseband data. A programmable FIFO depth
interrupt simplifies the interface to the I and Q input FIFOs.
Block Diagram
Features
• Output Sample Rates Up to 104MSPS with Input Data
Rates Up to 6.5MSPS
• Processing Capable of >140dB SFDR Out of Band
• Vector modulation for supporting IS-136, EDGE, IS95, TD-
SCDMA, CDMA-2000-1X/3X, W-CDMA, and UMTS
• FM Modulation for Supporting AMPS, NMT, and GSM
• Four Completely Independent Channels on Chip, Each With
Programmable 256 Tap Shaping FIR, Half-Band, and High
Order Interpolation Filters
• 16-Bit parallel µProcessor Interface and Four Independent
Serial Data Inputs
• Two 20-bit I/O Buses and Two 20-bit Output Buses Allow
Cascading Multiple Devices
• 32-Bit Programmable Carrier NCO; 48-Bit Programmable
Symbol Timing NCOs
• Dynamic Gain Profiling and Output Routing Control
Applications
• Single or Multiple Channel Digital Software Radio
Transmitters (Wide-Band or Narrow-Band)
• Base Station Transmitter and Smart Antennas
• Operates with HSP50216 in Software Radio Solutions
• Compatible with the HI5960/ISL5961 or HI5828/ISL5929
D/A Converters
Ordering Information
PART
NUMBER
ISL5217KI
ISL5217EVAL1
TEMP
RANGE (oC) PACKAGE
-40 to 85 196 Ld BGA
25 Evaluation Kit
PKG. NO
V196.15x15
SDA
SDB INPUT I/Q SHAPING I/Q I/Q HALF I/Q INTPL I/Q COMPLEX I/Q
SDC
SDD
DATA
FILTER/
FM MOD.
BAND
FILTER
MIXER
SIN COS
CARRIER
NCO
SAMPLE
NCO
CHANNEL 0
CHANNEL 1
P<15:0>
A<6:0>
{CNTRL}
PARALLEL HOST INTERFACE
CHANNEL 2
CHANNEL 3
CONFIGURATION AND CONTROL BUS
I0
Q0 4 CH
I1 SUM
ΣQ1
I2
Q2
ΣI3
Q3 1
Σ2
Σ3
Σ4
DELAY
SUM
CAS IOUT(19:0)
SUM
CAS
SUM QOUT(19:0)
QIN(19:0)
IIN(19:0)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. CommLink™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL5217 pdf, ピン配列
ISL5217
Pinout
196 LdBGA
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
IOUT14 IOUT13 IOUT12 IOUT10 GND IOUT8 IOUT6 IOUT4 IOUT2 VCCIO IOUT0 P15 P12 P11
B
IOUT16 IOUT15 IOUT11 VCCIO IOUT9 GND IOUT5 IOUT3 VCCIO IOUT1 GND P13 P10
P9
C
IOUT18 IOUT17 QOUT16 QOUT15 QOUT12 QOUT9 IOUT7 GND QOUT3 QOUT0 GND P14
P8
P6
D
IOUT19 GND GND VCCIO QOUT13 QOUT10 VCCC QOUT6 QOUT4 QOUT1 VCCC
P7 VCCC P4
E
VCCC QOUT17 QOUT18 RESET QOUT14 QOUT11 QOUT8 QOUT7 QOUT5 QOUT2 P2
P5
P3 GND
F
ISTRB VCCC QOUT19 TRITST OUTEN1
A6
P0 GND
P1
A5
G
CLK QIN19 GND VCCC OUTEN0
H
TCK QIN17 QIN18 TMS TRST
J
IIN19 GND QIN16 TDI TDO
A1 VCCC A3 A4 A2
A0
CS GND WR
RD
SYNCO FSRC FSRB VCCC FSRD
K
GND QIN15 QIN14 QIN12 OFFBIN QIN9 QIN7 QIN5 QIN3 FSRA UPDA UPDD UPDC VCCC
L
IIN18 VCCIO QIN13 VCCIO QIN11 QIN8 QIN6 VCCC QIN2 RDMODE VCCIO GND GND SCLKD
M
IIN16 IIN17 IIN11 GND QIN10 IIN5 GND QIN4 QIN1 SDB SDD UPDB TXEND SCLKC
N
IIN14 IIN15 IIN9 GND IIN7 VCCC IIN3 IIN1 GND QIN0 VCCIO TXENA TXENC SCLKB
P
IIN13 IIN12 IIN10 IIN8 VCCC IIN6
IIN4 IIN2 IIN0 GND SDA SDC TXENB SCLKA
POWER PIN
SIGNAL PIN
GROUND PIN
THERMAL BALL
NOTE:
Thermal balls should be connected to the ground plane.
NC (NO CONNECTION)
3


3Pages


ISL5217 電子部品, 半導体
ISL5217
Functional Description
The ISL5217 Quad Programmable UpConverter (QPUC)
converts digital baseband data into modulated or frequency
translated digital samples. The QPUC can be configured to
create any quadrature amplitude shift-keyed (QASK) data
modulated signal, including QPSK, BPSK, and m-ary QAM.
The QPUC can also be configured to create both shaped
and unfiltered FM signals. A minimum of 16 bits of resolution
is maintained throughout the internal processing.
The QPUC is configured via the microprocessor data bus,
using the A<6:0> address bus, P<15:0> data bus, RD, WR
and CS control signals. Configuration data that is loaded via
this bus includes the individual channel’s 48-bit Sample Rate
NCO center frequency, the 32-bit Carrier NCO center
frequency, the device modulation format, gain control, input
mode control, reset control and sync control. The I and Q
baseband channels each have a 256 tap FIR filter whose
coefficients and configuration are also programmed via the
µP interface. Similarly, the control signals for the I and Q
channel interpolation filters are programmed via the µP
interface. Discussion in the following sections utilizes the
register definitions for channel 0. Channels 1-3 are similarly
configured in accordance with the Table 10 Memory Map.
Data Input
The I/Q sample pairs can be input serially through 1 of 4
serial interfaces or in parallel through the µP addressable
registers as shown in Figure 1.
0x11, 1:0
0x11, 3:2
0x12, 9:0
0x13, 9:0
0x11, 15
SDA
SDB
SDC
SDD
I sample (15:0)
A<6:0>
P<15:0>
0x0, 15:0
0x1, 15:0
Q sample (15:0)
FIGURE 1. SINGLE CHANNEL DATA INPUT PATH
back 16-bit serial transfers can occur by setting control word
(0x17, bits 14:13) both high. The serial process begins with the
first serial clock after the start of a sample clock. The frame
strobe is asserted for one serial clock and starts the I and Q
time slot counters. The TXENX pin or Main control (0X0c, bit 0)
S/W TX enable must be asserted to enable the frame strobe
out. Additional requests for serial data, with TXENX de-
asserted, are controlled by bit 3 of control word 0x0c. The serial
interface may be programmed to be dependent or independent
of TXENX control. The I and Q time slot counters, programmed
through 0x12, bits 9:0 and 0x13, bits 9:0, control the duration of
the serial to parallel conversion of the serial data input. The
counters are loaded to count the number of serial clocks from
the frame strobe to shift in the last data bit of that sample. The
time slot counters are 10-bits to allow multiple channels to
share a common serial data input. The MSB is always shifted
first, but the order of the I and Q serial data is flexible due to the
variability of the time slot counters. The received serial word is
MSB justified prior to loading into the FIFO holding register
based on the serial word length, programed through Serial
control (0x11, bits 3:2) to 4, 8, 12, or 16 bits.
Although each channel has control of a serial interface it may
select serial data from one of the other interfaces. Serial
control (0x11, bits 1:0) selects 1 of 4 serial data ports for the
channel. The serial data transfer format is shown in Figure 2.
SCLKX
UPDX
TXENX
FSRBX
INACTIVE
SDX
DON’T CARE
FIGURE 2. SERIAL DATA TRANSFER
The ability to select the serial input source allows multiple
QPUCs to share a single microprocessor interface with their
processing synchronized through the master QPUC SYNCO
being tied to the slave device UPDX. Conversely, multiple
Serial
The serial mode allows the device to shift the I and Q samples
serially into the FIFO holding registers. The serial input format
is selected when Serial control (0x11, bit 15) is high. The serial
interface is three-wire interface controlled by the channel. The
serial clock and frame strobe are driven by the channel to clock
the serial data from the source into the serial data port. The
serial clock can operate at the clock rate, at a divided clock rate,
or be driven at 32x the sample clock rate. Serial control (0x11,
bits 13:8) configure the serial clock. In the 32x mode, back to
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共有リンク

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部品番号部品説明メーカ
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ISL5217

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