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PDF ISL5216 Data sheet ( Hoja de datos )
| Número de pieza | ISL5216 | |
| Descripción | Four-Channel Programmable Digital DownConverter | |
| Fabricantes | Intersil Corporation | |
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TM
Data Sheet
February 2002
ISL5216
FN6013.1
Four-Channel Programmable Digital
DownConverter
The ISL5216 Quad Programmable Digital DownConverter
(QPDC) is designed for high dynamic range applications
such as cellular basestations where multiple channel
processing is required in a small physical space. The QPDC
combines into a single package a set of four channels which
include: digital mixers, a quadrature carrier NCO, digital
filters, a resampling filter, a Cartesian-to-polar coordinate
converter and an AGC loop.
The ISL5216 accepts four channels of 16-bit fixed or up to
14-bit mantissa / 3-bit exponent floating point real or
complex digitized IF samples which are mixed with local
quadrature sinusoids. Each channel carrier NCO frequency
is set independently by the microprocessor. The output of
the mixers are filtered with a CIC and FIR filters, with a
variety of decimation options. Gain adjustment is provided
on the filtered signal. The digital AGC provides a gain adjust
range of up to 96dB with programmable thresholds and slew
rates. A cartesian to polar coordinate converter provides
magnitude and phase outputs. A frequency discriminator is
also provided to allow FM demodulation. Selectable outputs
include I samples, Q samples, Magnitude, Phase, Frequency
and AGC gain. The output resolution is selectable from 4-bit
fixed point to 32-bit floating point.
Output bandwidths in excess of 1 MHz are achievable using
a single channel. Wider bandwidths are available by
cascading or polyphasing multiple channels.
Features
• Up to 95MSPS Input
• Four Independently Programmable Downconverter
Channels in a single package
• Four Parallel 17-Bit Inputs providing 16-bit fixed or one of
several 17-bit floating point formats
• 32-Bit Programmable Carrier NCO with > 115dB SFDR
• 110dB FIR Out of Band Attenuation
• Decimation from 4 to >65536
• 24-bit Internal Data Path
• Digital AGC with up to 96dB of Gain Range
• Filter Functions
- 1- to 5-Stage CIC Filter
- Halfband Decimation and Interpolation FIR Filtering
- Programmable FIR Filtering
- Resampling FIR Filtering
• Cascadable Filtering for Additional Bandwidth
• Four Independent Serial Outputs
• 2.5V Core, 3.3V I/O Operation
Applications
• Narrow-Band TDMA through IS-95 CDMA Digital Software
Radio and Basestation Receivers
• Wide-Band Applications: W-CDMA and UMTS Digital
Software Radio and Basestation Receivers
Ordering Information
PART
NUMBER
TEMP
RANGE (oC)
PACKAGE
PKG. NO
ISL5216KI
ISL5216KI-1
-40 to 85
-40 to 85
196 Ld 0.8 mm V196.12x12
BGA
196 Ld 1.0 mm V196.15x15
BGA
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1 page  
ISL5216
Pin Descriptions (Continued)
NAME
TYPE
DESCRIPTION
SYNCI3
I Synchronization input signal for channel 3. Same functions as SYNCI but connects only to channel 3. This pin
is internally pulled low to allow it to be left unconnected.
SYNCO
O Synchronization Output Signal. The processing of multiple ISL5216 or HSP50216 devices can be
synchronized by tying the SYNCO from one ISL5216 device (the master) to the SYNCI of all the ISL5216 /
HSP50216 devices (the master and slaves).
RESET
I Reset Signal. Active low. Asserting reset will halt all processing and set certain registers to default values.
JTAG
TDO
O Test data out
TDI I Test data in. Contains weak internal pull up.
TMS
I Test mode select. Contains weak internal pull up.
TCLK
I Test clock. Contains weak internal pull down.
TRST
I Test reset. Active low. Contains weak internal pull down.
OUTPUTS
SD1A
O Serial Data Output 1A. A serial data stream output which can be programmed to consist of I1, Q1, I2, Q2,
magnitude, phase, frequency (dφ/dt), AGC gain, and/or zeros. In addition, data outputs from Channels 0, 1, 2
and 3 can be multiplexed into a common serial output data stream. Information can be sequenced in a
programmable order. See Serial Data Output Formatter Section and Microprocessor Interface Section.
SD2A
O Serial Data Output 2A. This output is provided as an auxiliary output for Serial Data Output 1A to route data
to a second destination or to output two words at a time for higher sample rates. SD2A has the same
programmability as SD1A except that floating point format is not available. See Serial Data Output Formatter
Section and Microprocessor Interface Section.
SD1B
O Serial Data Output 1B. See description for SD1A.
SD2B
O Serial Data Output 2B. See description for SD2A.
SD1C
O Serial Data Output 1C. See description for SD1A.
SD2C
O Serial Data Output 2C. See description for SD2A.
SD1D
O Serial Data Output 1D. See description for SD1A.
SD2D
O Serial Data Output 2D. See description for SD2A.
SCLK
O Serial Output Clock. Can be programmed to be at 1, 1/2, 1/4, 1/8, or 1/16 times the clock frequency. The
polarity of SCLK is programmable.
SYNCA
O Serial Data Output 1A sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCA is programmable.
SYNCB
O Serial Data Output 1B sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCB is programmable.
SYNCC
O Serial Data Output 1C sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCC is programmable.
SYNCD
O Serial Data Output 1D sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCD is programmable.
MICROPROCESSOR INTERFACE
P(15:0)
I/O Microprocessor Interface Data bus. See Microprocessor Interface Section. P15 is the MSB.
ADD(2:0)
I Microprocessor Interface Address bus. ADD2 is the MSB. See Microprocessor Interface Section. Note: ADD2
is not used but designated for future expansion.
WR
or
DSTRB
I Microprocessor Interface Write or Data Strobe Signal. When the Microprocessor Interface Mode Control, µP
MODE, is a low data transfers (from either P(15:0) to the internal write holding register or from the internal write
holding register to the target register specified) occur on the low to high transition of WR when CE is asserted
(low). When the µP MODE control is high this input functions as a data read/write strobe. In this mode with
RD/WR low data transfers (from either P(15:0) to the internal write holding register or from the internal write
holding register to the target register specified) occur on the low to high transition of Data Strobe. With RD/WR
high the data from the address specified is placed on P(15:0) when Data Strobe is low. See Microprocessor
Interface Section.
5
5 Page 
ISL5216
clock and Q * (-SIN) and Q * COS on the second clock cycle.
The first integrator of the CIC is enabled on both clock cycles
to add the two products. The rest of the stages are enabled
only on the first cycle.
In complex input mode, the input level detector uses only I
samples for its magnitude computation.
The CIC decimation counter is programmed for two times
the number of complex input samples. The exponent input
must be the same for I and Q for the floating point modes.
See IWA *000h for details on controlling the complex input
mode.
NCO / Mixer
After the input select/format section, the samples are
multiplied by quadrature sine wave samples from the carrier
NCO. The NCO has a 32-bit frequency control, providing
sub-hertz resolution at the maximum clock rate. The
quadrature sinusoids have exceptional purity. The purity of
the NCO should not be the determining factor for the
receiver dynamic range performance. The phase
quantization to the sine/cosine generator is 24 bits and the
amplitude quantization is 19 bits.
The carrier NCO center frequency is loaded via the µP bus.
The center frequency control is double buffered - the input
is loaded into a center frequency holding register via the µP
interface. The data is then transferred from the holding
register to the active register by a write to a address IWA
*006h or by a SYNCI signal, if loading via SYNCI is
enabled. To synchronize multiple channels, the carrier NCO
phase accumulator feedback can be zeroed on loading to
restart all of the NCOs at the same phase. A serial offset
frequency input is also available for each channel through
the D(15:0) parallel data input bus (if that bus is not needed
for data input). This is legacy support for HSP50210 type
tracking signals. See IWA=*000 and *004 for carrier offset
frequency parameters.
After the mixers, a PN (pseudo noise) signal can be added to
the data. This feature is provided for test and to digitally
reduce the input sensitivity and adjust the receiver range
(sensitivity). The effect is the same as increasing the noise
figure of the receiver, reducing its sensitivity and overall
dynamic range. For testing, the PN generator provides a
wideband signal which may be used to verify the frequency
response of a filter. The one bit PN data is scaled by a 16-bit
programmable scale factor. The overall range for the PN is 0
to 1/4 full scale (see IWA = *001h). A gain of 0 disables the
PN input. The PN value is formed as:
PN VALUE
2-3 2-4 . . . . . . . . . . . . 2-17 2-18
SSS X X XXXXXXXXXXXX X X
where S is the sign extension of the 16 bit PN gain register
value (IWA = *001H) times the PN chip value and the 16 X’s
refer to the PN gain register times the PN chip value.
The minimum, non-zero, PN value is 2-18 of full scale
(-108dBFS) on each axis (-105dBFS total). For an input noise
level of -75dBFS, this allows the SNR to be decreased in
steps of 1/8dB or less. The I and Q PN codes are offset in time
to decorrelate them. The PN code is selected and enabled in
the test control register (F800h). The PN is added to the signal
after the mix with the three sign bits aligned with the most
significant three bits of the signal, so the maximum level is -
12dBFS and the minimum, non-zero level is -108dBFS. The
PN code can be 215-1, 223-1 or 215-1 * 223-1.
CIC Filter
Next, the signal is filtered by a cascaded integrator/comb
(CIC) filter. A CIC filter is an efficient architecture for
decimation filtering. The power or magnitude squared
frequency response of the CIC filter is given by:
2N
P(f)
=
-s---i-n----(---π---M------f--)
sin
π-R---f
where
M = Number of delays (1 for the ISL5216)
N = Number of stages
and R = Decimation factor.
The passband frequency response for first (N=1) though fifth
(N=5) order CIC filters is plotted in Figure 13. The frequency
axis is normalized to fS/R, making fS/R = 1 the CIC output
sample rate. Figure 15 shows the frequency response for a
5th order filter but extends the frequency axis to fS/R = 3
(3 times the CIC output sample rate) to show alias rejection
for the out of band signals. Figure 14 uses information from
Figure 15 to provide the amplitude of the first (strongest)
alias as a function of the signal frequency or bandwidth from
DC. For example, with a 5th order CIC and fS/R = 0.125
(signal frequency is 1/8 the CIC output rate) Figure 14 shows
a first alias level of about -87 dB. Figure 14 is also listed in
table form in Table 51 (CIC Passband and Alias Levels).
The CIC filter order is programmable from 0 to 5. The CIC
may be bypassed by setting the CIC filter order to 0
(IWA = *004h bits 13:9 are all set equal to 1) and the CIC
barrel shift (IWA = *004h bits 19:14) to 45 decimal. The CIC
output rate must, however, be no more than CLKmax / 4
where CLKmax is the maximum clock frequency available on
the device (see electrical specifications section).
The integrator bit widths are 69, 62, 53, 44, and 34 for the
firstt through fifth stages, respectively, while the comb bit
widths are all 32. The integrators are sized for decimation
factors of up to 512 with five stages, 2048 with four stages,
32768 with three stages, and 65536 with one or two stages.
Higher decimations in the CIC should be avoided as they
will cause integrator overflow. In the ISL5216, the
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL5216.PDF ] | |
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