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IS82C37A の電気的特性と機能

IS82C37AのメーカーはIntersil Corporationです、この部品の機能は「CMOS High Performance Programmable DMA Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS82C37A
部品説明 CMOS High Performance Programmable DMA Controller
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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IS82C37A Datasheet, IS82C37A PDF,ピン配置, 機能
82C37A
March 1997
CMOS High Performance
Programmable DMA Controller
Features
Description
• Compatible with the NMOS 8237A
• Four Independent Maskable Channels with Autoinitial-
ization Capability
• Cascadable to any Number of Channels
• High Speed Data Transfers:
- Up to 4MBytes/sec with 8MHz Clock
- Up to 6.25MBytes/sec with 12.5MHz Clock
• Memory-to-Memory Transfers
• Static CMOS Design Permits Low Power Operation
- ICCSB = 10µA Maximum
- ICCOP = 2mA/MHz Maximum
• Fully TTL/CMOS Compatible
• Internal Registers may be Read from Software
The 82C37A is an enhanced version of the industry standard
8237A Direct Memory Access (DMA) controller, fabricated
using Intersil’s advanced 2 micron CMOS process. Pin
compatible with NMOS designs, the 82C37A offers
increased functionality, improved performance, and
dramatically reduced power consumption. The fully static
design permits gated clock operation for even further
reduction of power.
The 82C37A controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
The 82C37A is designed to be used with an external
address latch, such as the 82C82, to demultiplex the most
significant 8-bits of address. The 82C37A can be used with
industry standard microprocessors such as 80C286, 80286,
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and
others. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
Ordering Information
5MHz
CP82C37A-5
IP82C37A-5
CS82C37A-5
IS82C37A-5
CD82C37A-5
ID82C37A-5
MD82C37A-5/B
5962-9054301MQA
MR82C37A-5/B
5962-9054301MXA
PART NUMBER
8MHz
CP82C37A
IP82C37A
CS82C37A
IS82C37A
CD82C37A
ID82C37A
MD82C37A/B
5962-9054302MQA
MR82C37A/B
5962-9054302MXA
12.5MHz
CP82C37A-12
IP82C37A-12
CS82C37A-12
IS82C37A-12
CD82C37A-12
ID82C37A-12
MD82C37A-12/B
5962-9054303MQA
MR82C37A-12/B
5962-9054303MXA
PACKAGE
40 Ld PDIP
44 Ld PLCC
40 Ld CERDIP
SMD#
44 Pad CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG. NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-192
File Number 2967.1

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IS82C37A pdf, ピン配列
82C37A
Pin Description
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
VCC
31
VCC: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for
decoupling.
GND
20
Ground
CLK 12 I CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A
operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for
the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for
standby operation.
CS 11 I CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for
CPU communications.
RESET
13
READY
6
HLDA
7
DREQ0-
DREQ3
16-19
DB0-DB7
21-23
26-30
IOR 1
IOW 2
I RESET: This is an active high input which clears the Command, Status, Request, and Temporary
registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore
requests. Following a Reset, the controller is in an idle cycle.
I READY: This signal can be used to extend the memory read and write pulses from the 82C37A to
accommodate slow memories or I/O devices. READY must not make transitions during its specified
set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode.
I HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has
relinquished control of the system busses. HLDA is a synchronous input and must not transition
during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising
edge of CLK, during which time HLDA must not transition.
I DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request
inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest
priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a
channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is
programmable. RESET initializes these lines to active high. DREQ must be maintained until the
corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused
DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set.
I/O DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data
bus. The outputs are enabled in the Program condition during the I/O Read to output the contents
of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle
when the CPU is programming the 82C37A control registers. During DMA cycles, the most signifi-
cant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB.
In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during
the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write
the data into the new memory location.
I/O I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control
signal used by the 82C37A to access data from the peripheral during a DMA Write transfer.
I/O I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output
control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.
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IS82C37A 電子部品, 半導体
82C37A
The 82C37A can assume seven separate states, each
composed of one full clock period. State I (SI) is the idle
state. It is entered when the 82C37A has no valid DMA
requests pending, at the end of a transfer sequence, or
when a Reset or Master Clear has occurred. While in SI, the
DMA controller is inactive but may be in the Program
Condition (being programmed by the processor).
State 0 (S0) is the first state of a DMA service. The 82C37A
has requested a hold but the processor has not yet returned
an acknowledge. The 82C37A may still be programmed until
it has received HLDA from the CPU. An acknowledge from
the CPU will signal the DMA transfer may begin. S1, S2, S3,
and S4 are the working state of the DMA service. If more
time is needed to complete a transfer than is available with
normal timing, wait states (SW) can be inserted between S3
and S4 in normal transfers by the use of the Ready line on
the 82C37A. For compressed transfers, wait states can be
inserted between S2 and S4. See timing Figures 14 and 15.
Note that the data is transferred directly from the I/O device
to memory (or vice versa) with IOR and MEMW (or MEMR
and IOW) being active at the same time. The data is not read
into or driven out of the 82C37A in I/O-to-memory or
memory-to-I/O DMA transfers.
Memory-to-memory transfers require a read-from and a write-
to memory to complete each transfer. The states, which
resemble the normal working states, use two-digit numbers
for identification. Eight states are required for a single transfer.
The first four states (S11, S12, S13, S14) are used for the
read-from-memory half and the last four state (S21, S22, S23,
S24) for the write-to-memory half of the transfer.
Idle Cycle
Special software commands can be executed by the
82C37A in the Program Condition. These commands are
decoded as sets of addresses with CS, IOR, and IOW. The
commands do not make use of the data bus. Instructions
include Set and Clear First/Last Flip-Flop, Master Clear,
Clear Mode Register Counter, and Clear Mask Register.
Active Cycle
When the 82C37A is in the Idle cycle, and a software
request or an unmasked channel requests a DMA service,
the device will issue HRQ to the microprocessor and enter
the Active cycle. It is in this cycle that the DMA service will
take place, in one of four modes:
Single Transfer Mode - In Single Transfer mode, the device
is programmed to make one transfer only. The word count
will be decremented and the address decremented or
incremented following each transfer. When the word count
“rolls over” from zero to FFFFH, a terminal count bit in the
status register is set, an EOP pulse is generated, and the
channel will autoinitialize if this option has been selected. If
not programmed to autoinitialize, the mask bit will be set,
along with the TC bit and EOP pulse.
DREQ must be held active until DACK becomes active. If
DREQ is held active throughout the single transfer, HRQ will
go inactive and release the bus to the system. It will again go
active and, upon receipt of a new HLDA, another single
transfer will be performed, unless a higher priority channel
takes over. In 8080A, 8085A, 80C88, or 80C86 systems, this
will ensure one full machine cycle execution between DMA
transfers. Details of timing between the 82C37A and other
bus control protocols will depend upon the characteristics of
the microprocessor involved.
When no channel is requesting service, the 82C37A will
enter the idle cycle and perform “SI” states. In this cycle, the
82C37A will sample the DREQ lines on the falling edge of
every clock cycle to determine if any channel is requesting a
DMA service.
Note that for standby operation where the clock has been
stopped, DMA requests will be ignored. The device will
respond to CS (chip select), in case of an attempt by the
microprocessor to write or read the internal registers of the
82C37A. When CS is low and HLDA is low, the 82C37A
enters the Program Condition. The CPU can now establish,
change or inspect the internal definition of the part by read-
ing from or writing to the internal registers.
The 82C37A may be programmed with the clock stopped, pro-
vided that HLDA is low and at least one rising clock edge has
occurred after HLDA was driven low, so the controller is in an SI
state. Address lines A0-A3 are inputs to the device and select
which registers will be read or written. The IOR and IOW lines
are used to select and time the read or write operations. Due to
the number and size of the internal registers, an internal flip-flop
called the First/Last Flip-Flop is used to generate an additional
bit of address. The bit is used to determine the upper or lower
byte of the 16-bit Address and Work Count registers. The flip-
flop is reset by Master Clear or RESET. Separate software
commands can also set or reset this flip-flop.
Block Transfer Mode - In Block Transfer mode, the device
is activated by DREQ or software request and continues
making transfers during the service until a TC, caused by
word count going to FFFFH, or an external End of Process
(EOP) is encountered. DREQ need only be held active until
DACK becomes active. Again, an Autoinitialization will occur
at the end of the service if the channel has been
programmed for that option.
Demand Transfer Mode - In Demand Transfer mode the
device continues making transfers until a TC or external EOP is
encountered, or until DREQ goes inactive. Thus, transfer may
continue until the I/O device has exhausted its data capacity.
After the I/O device has had a chance to catch up, the DMA
service is reestablished by means of a DREQ. During the time
between services when the microprocessor is allowed to oper-
ate, the intermediate values of address and word count are
stored in the 82C37A Current Address and Current Word
Count registers. Higher priority channels may intervene in the
demand process, once DREQ has gone inactive. Only an EOP
can cause an Autoinitialization at the end of service. EOP is
generated either by TC or by an external signal.
Cascade Mode - This mode is used to cascade more than
one 82C37A for simple system expansion. The HRQ and
HLDA signals from the additional 82C37A are connected to
the DREQ and DACK signals respectively of a channel for
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共有リンク

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部品番号部品説明メーカ
IS82C37A

CMOS High Performance Programmable DMA Controller

Intersil Corporation
Intersil Corporation
IS82C37A

CMOS High Performance Programmable DMA Controller

Harris Corporation
Harris Corporation
IS82C37A-12

CMOS High Performance Programmable DMA Controller

Intersil Corporation
Intersil Corporation
IS82C37A-12

CMOS High Performance Programmable DMA Controller

Harris Corporation
Harris Corporation


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