DataSheet.jp

IS80C88-2 の電気的特性と機能

IS80C88-2のメーカーはIntersil Corporationです、この部品の機能は「CMOS 8/16-Bit Microprocessor」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS80C88-2
部品説明 CMOS 8/16-Bit Microprocessor
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




このページの下部にプレビューとIS80C88-2ダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

IS80C88-2 Datasheet, IS80C88-2 PDF,ピン配置, 機能
80C88
March 1997
CMOS 8/16-Bit Microprocessor
[ /Title
(80C88
)
/Sub-
ject
(CMO
S 8/16-
Bit
Micro-
proces-
sor)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
8/16
Bit uP,
micro-
proces-
sor, 8
bit, 16
bit, 8-
bit, 16-
bit,
8088,
PC)
/Cre-
ator ()
Features
Description
• Compatible with NMOS 8088
• Direct Software Compatibility with 80C86, 8086, 8088
• 8-Bit Data Bus Interface; 16-Bit Internal Architecture
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88)
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C88-2)
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . 500µA Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . 10mA/MHz Maximum
• 1 Megabyte of Direct Memory Addressing Capability
The Intersil 80C88 high performance 8/16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
cess (Scaled SAJI IV). Two modes of operation, MINimum
for small systems and MAXimum for larger applications such
as multiprocessing, allow user configuration to achieve the
highest performance level.
Full TTL compatibility (with the exception of CLOCK) and
industry-standard operation allow use of existing NMOS
8088 hardware and Intersil CMOS peripherals.
Complete software compatibility with the 80C86, 8086, and
8088 microprocessors allows use of existing software in new
designs.
• 24 Operand Addressing Modes
• Bit, Byte, Word, and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
• Bus-Hold Circuitry Eliminates Pull-up Resistors
• Wide Operating Temperature Ranges
- C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to + 70oC
- I80C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M80C88 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
PACKAGE
Plastic DIP
PLCC
CERDIP
SMD#
LCC
SMD#
TEMPERATURE RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
5MHz
CP80C88
IP80C88
CS80C88
lS80C88
CD80C88
ID80C88
MD80C88/B
5962-8601601QA
MR80C88/B
5962-8601601XA
8MHz
CP80C88-2
IP80C88-2
CS80C88-2
IS80C88-2
CD80C88-2
ID80C88-2
MD80C88-2/B
-
MR80C88-2/B
-
PKG. NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
J44.A
J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-1
File Number 2949.1

1 Page





IS80C88-2 pdf, ピン配列
Functional Diagram
EXECUTION UNIT
REGISTER FILE
DATA POINTER
AND
INDEX REGS
(8 WORDS)
80C88
BUS INTERFACE UNIT
RELOCATION
REGISTER FILE
SEGMENT REGISTERS
AND
INSTRUCTION POINTER
(5 WORDS)
16-BIT ALU
FLAGS
BUS
INTERFACE
UNIT
SSO/HIGH
4 A19/S6. . . A16/S3
8 AD7-AD0
8 A8-A15
3 INTA, RD, WR
4 DT/R, DEN, ALE, IO/M
TEST
INTR
NMI
RQ/GT0, 1
HOLD
HLDA
2
4-BYTE
INSTRUCTION
QUEUE
CONTROL AND TIMING
LOCK
2 QS0, QS1
3 S2, S1, S0
CLK
3
RESET READY MN/MX GND
VCC
MEMORY INTERFACE
C-BUS
BUS
INTERFACE
UNIT
B-BUS
ES
CS
SS
DS
IP
INSTRUCTION
STREAM BYTE
QUEUE
A-BUS
EXECUTION UNIT
CONTROL SYSTEM
EXECUTION
UNIT
AH AL
BH BL
CH CL
DH DL
SP
BP
SI
DI
ARITHMETIC/
LOGIC UNIT
FLAGS
3-3


3Pages


IS80C88-2 電子部品, 半導体
80C88
Pin Description (Continued)
The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions
which are unique to the maximum mode are described; all other pin functions are as described above.
MAXIMUM MODE SYSTEM
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
S0 26 O STATUS: is active during clock high of T4, T1 and
S1 27 O T2, and is returned to the passive state (1, 1, 1) S2 S1 S0 CHARACTERISTICS
S2 28 O during T3 or during Tw when READY is HIGH. This 0 0 0 Interrupt Acknowledge
status is used by the 82C88 bus controller to gener-
ate all memory and I/O access control signals. Any
0
0
1 Read I/O Port
change by S2, S1 or S0 during T4 is used to 0 1 0 Write I/O Port
indicate the beginning of a bus cycle, and the return 0 1 1 Halt
to the passive state in T3 or Tw is used to indicate
the end of a bus cycle.
1 0 0 Code Access
These signals are held at a high impedance logic 1 0 1 Read Memory
one state during “grant sequence”.
1 1 0 Write Memory
1 1 1 Passive
RQ/GT0,
RQ/GT1
31
30
LOCK
29
QS1, QS0 24, 25
I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the
local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0
having higher priority than RQ/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may
be left unconnected. The request/grant sequence is as follows (see RQ/GT Timing Sequence):
1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to
the 80C88 (pulse 1).
2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88 to the requesting master
(pulse 2), indicates that the 80C88 has allowed the local bus to float and that it will enter the
“grant sequence” state at the next CLK. The CPUs bus interface unit is disconnected logically
from the local bus during “grant sequence”.
3. A pulse one CLK wide from the requesting master indicates to the 80C88 (pulse 3) that the “hold”
request is about to end and that the 80C88 can reclaim the local bus at the next CLK. The CPU
then enters T4 (or T1 if no bus cycles pending).
Each master-master exchange of the local bus is a sequence of three pulses. There must be one
idle CLK cycle after bus exchange. Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle, it will release the local bus during
T4 of the cycle when all the following conjugations are met:
1. Request occurs on or before T2.
2. Current cycle is not the low bit of a word.
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle
apply with condition number 1 already satisfied.
O LOCK: indicates that other system bus masters are not to gain control of the system bus while
LOCK is active (LOW). The LOCK signal is activated by the “LOCK” prefix instruction and remains
active until the completion of the next instruction. This signal is active LOW, and is held at a high
impedance logic one state during “grant sequence”. In Max Mode, LOCK is automatically generated
during T2 of the first INTA cycle and removed during T2 of the second INTA cycle.
O QUEUE STATUS: provide status to allow external
tracking of the internal 80C88 instruction queue.
QS1 QS0 CHARACTERISTICS
The queue status is valid during the CLK cycle after
which the queue operation is performed. Note that
the queue status never goes to a high impedance
statue (floated).
0 0 No Operation
0 1 First Byte of Opcode from
Queue
1 0 Empty the Queue
1 1 Subsequent Byte from
Queue
- 34 O Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during
a “grant sequence”.
3-6

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ IS80C88-2 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
IS80C88-2

CMOS 8/16-Bit Microprocessor

Intersil Corporation
Intersil Corporation


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap