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IS63LV1024-8TI の電気的特性と機能

IS63LV1024-8TIのメーカーはIntegrated Silicon Solution Incです、この部品の機能は「128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS63LV1024-8TI
部品説明 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT
メーカ Integrated Silicon Solution Inc
ロゴ Integrated Silicon Solution  Inc ロゴ 




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IS63LV1024-8TI Datasheet, IS63LV1024-8TI PDF,ピン配置, 機能
IS63LV1024
ISSI®
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
SEPTEMBER 2000
FEATURES
• High-speed access times:
8, 10, 12 and 15 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 32-pin 300-mil SOJ
– 32-pin 400-mil SOJ
– 32-pin TSOP (Type II)
DESCRIPTION
The ISSI IS63LV1024 is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The IS63LV1024 is fabricated using ISSI's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS63LV1024 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
VCC
GND
I/O0-I/O7
DECODER
128K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
CE
CONTROL
OE CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
1

1 Page





IS63LV1024-8TI pdf, ピン配列
IS63LV1024
ISSI ®
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
40°C to +85°C
VCC
3.3V ± 0.3V
3.3V ± 0.15V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage(1)
ILI Input Leakage
Test Conditions
VCC = Min., IOH = 4.0 mA
VCC = Min., IOL = 8.0 mA
GND VIN VCC
ILO Output Leakage
GND VOUT VCC, Outputs Disabled
Notes:
1. VIL = 3.0V for pulse width less than 10 ns.
Com.
Ind.
Com.
Ind.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Min.
2.4
2.2
0.3
1
5
1
5
Max.
0.4
VCC + 0.3
0.8
1
5
1
5
Unit
V
V
V
V
µA
µA
Symbol Parameter
ICC1 Vcc Operating
Supply Current
ISB TTL Standby
Current
(TTL Inputs)
ISB1 TTL Standby
Current
(TTL Inputs)
ISB2 CMOS Standby
Current
Test Conditions
VCC = Max., CE = VIL
IOUT = 0 mA, f = Max.
VCC = Max.,
VIN = VIH or VIL
CE VIH, f = Max
VCC = Max.,
VIN = VIH or VIL
CE VIH, f = 0
VCC = Max.,
CE VCC 0.2V,
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
-8 ns
Min. Max.
160
170
55
55
25
30
5
10
-10 ns
Min. Max.
150
160
45
45
25
30
5
10
-12 ns
Min. Max.
130
140
40
40
25
30
5
10
-15 ns
Min. Max.
120
130
35
35
Unit
mA
mA
25
30
mA
5
10
mA
(CMOS Inputs)
VIN VCC 0.2V, or
VIN 0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol Parameter
Conditions
Max.
CIN Input Capacitance
VIN = 0V
6
CI/O
Input/Output Capacitance
VOUT = 0V
8
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
Unit
pF
pF
3


3Pages


IS63LV1024-8TI 電子部品, 半導体
IS63LV1024
ISSI ®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
tWC
tSCE
tAW
tHA
tSA
tPWE1(1)
tPWE2(2)
tSD
tHD
tHZWE(2)
tLZWE(2)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time to
Write End
Address Hold from
Write End
Address Setup Time
WE Pulse Width (OE High)
WE Pulse Width (OE Low)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-8 ns
Min. Max.
8
7
8
0
0
7
8
5
0
4
3
-10 ns
Min. Max.
10
7
8
0
0
7
10
5
0
5
3
-12 ns
Min. Max.
12
8
8
0
0
8
12
6
0
6
3
-15 ns
Min. Max.
15
10
10
0
0
10
15
7
0
7
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)
t WC
ADDRESS
CE
WE
DOUT
DIN
VALID ADDRESS
t SA t SCE t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD t HD
DATAIN VALID
CE_WR1.eps
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00

6 Page



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部品番号部品説明メーカ
IS63LV1024-8T

128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS63LV1024-8TI

128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc


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