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PDF IS62LV256-70T Data sheet ( Hoja de datos )
| Número de pieza | IS62LV256-70T | |
| Descripción | 32K x 8 LOW VOLTAGE STATIC RAM | |
| Fabricantes | Integrated Silicon Solution Inc | |
| Logotipo |  |
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IS62LV256
ISSI®
32K x 8 LOW VOLTAGE STATIC RAM
DECEMBER 2002
FEATURES
• Access time: 45, 70 ns
• Low active power: 70 mW
• Low standby power
— 45 µW CMOS standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
DESCRIPTION
The ISSI IS62LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS double-metal technology.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
10 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE) input and an active LOW Output Enable
(OE) input. The active LOW Write Enable (WE) controls both
writing and reading of the memory.
The IS62LV256 is pin compatible with other 32K x 8 SRAMs
in 300-mil SOJ, 330-mil plastic SOP, and TSOP (Type I Normal
and Reverse Bent) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VCC
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
256 X 1024
MEMORY ARRAY
COLUMN I/O
CE
CONTROL
OE CIRCUIT
WE
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. K
12/11/02
1
1 page  
IS62LV256
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
5 ns
1.5V
See Figures 1a and 1b
ISSI ®
3.3V
1213 Ω
OUTPUT
100 pF
Including
jig and
scope
1378 Ω
3.3V
1213 Ω
OUTPUT
5 pF
Including
jig and
scope
1378 Ω
Figures 1a
Figures 1b
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
tRC
tAA
tOHA
tACE
tDOE
tLZOE(2)
tHZOE(2)
tLZCE(2)
tHZCE(2)
tPU(3)
tPD(3)
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power-Up
CE to Power-Down
-45 ns
Min. Max.
45 —
— 45
2—
— 45
— 25
0—
0 20
3—
0 20
0—
— 30
-70 ns
Min. Max.
70 —
— 70
2—
— 70
— 35
0—
0 25
3—
0 25
0—
— 50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. K
12/11/02
5
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