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PDF IS62LV12816L-70B Data sheet ( Hoja de datos )
| Número de pieza | IS62LV12816L-70B | |
| Descripción | 128K x 16 CMOS STATIC RAM | |
| Fabricantes | Integrated Silicon Solution Inc | |
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IS62LV12816L
IS62LV12816L
128K x 16 CMOS STATIC RAM
ISSISSII®®
ADVANCE INFORMATION
AUGUST 1998
FEATURES
• High-speed access time: 70, 100, and 120 ns
• CMOS low power operation
– 120 mW (typical) operating
– 6 µW (typical) CMOS standby
• TTL compatible interface levels
• Single 3V ± 10% VCC power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA
FUNCTIONAL BLOCK DIAGRAM
1
DESCRIPTION
2The ISSI IS62LV12816L is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated
using ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices.
3
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
4with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
5A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS62LV12816L is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA.
6
7
A0-A16
DECODER
128K x 16
MEMORY ARRAY
8
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
COLUMN I/O
9
10
11
12
The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
1
1 page  
IS62LV12816L
ISSI ®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
-70
Min. Max.
-100
Min. Max.
-120
Min. Max.
Unit
tRC Read Cycle Time
70 —
100 —
120 —
ns
tAA
Address Access Time
— 70
— 100
— 120
ns
tOHA
tACE
tDOE
tHZOE(2)
tLZOE(2)
tHZCE(2)
tLZCE(2)
tBA
tHZB
tLZB
Output Hold Time
CE Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
10
—
—
—
5
0
10
—
0
0
—
70
35
25
—
25
—
35
25
—
15 —
— 100
— 50
— 30
5—
0 30
10 —
— 50
0 35
0—
15 —
— 120
— 60
0 40
5—
0 40
10 —
— 60
0 50
0—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4 to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
1
2
3
4
5
6
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
ADDRESS
DOUT
tRC
PREVIOUS DATA VALID
tOHA
tAA
tOHA
DATA VALID
7
8
9
10
11
12
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IS62LV12816L-70B.PDF ] | |
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