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PDF IS62C256-70U Data sheet ( Hoja de datos )

Número de pieza IS62C256-70U
Descripción 32K x 8 LOW POWER CMOS STATIC RAM
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IS62C256
32K x 8 LOW POWER CMOS STATIC RAM
ISSI®
FEATURES
• Access time: 45, 70 ns
• Low active power: 200 mW (typical)
• Low standby power
— 250 µW (typical) CMOS standby
— 28 mW (typical) TTL standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V power supply
DESCRIPTION
The ISSI IS62C256 is a low power, 32,768 word by 8-bit
CMOS static RAM. It is fabricated using ISSI's high-
performance, low power CMOS technology.
When CS is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 µW (typical) at CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Select (CS) input and an active LOW Output Enable (OE)
input. The active LOW Write Enable (WE) controls both writing
and reading of the memory.
The IS62C256 is pin compatible with other 32K x 8 SRAMs in
plastic SOP or TSOP (Type I) package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VCC
GND
I/O0-I/O7
DECODER
32K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
CS
CONTROL
OE CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
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IS62C256-70U pdf
IS62C256
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
ADDRESS
DOUT
PREVIOUS DATA VALID
t OHA
t RC
t AA
ISSI®
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
ADDRESS
OE
CS
DOUT
t LZCS
HIGH-Z
t RC
t AA
t DOE
t LZOE
t ACS
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS = VIL.
3. Address is valid prior to or coincident with CS LOW transitions.
t OHA
t HZOE
t HZCS
DATA VALID
CS_RD2.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
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