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IS62C256-45U の電気的特性と機能

IS62C256-45UのメーカーはETCです、この部品の機能は「32K x 8 LOW POWER CMOS STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS62C256-45U
部品説明 32K x 8 LOW POWER CMOS STATIC RAM
メーカ ETC
ロゴ ETC ロゴ 




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IS62C256-45U Datasheet, IS62C256-45U PDF,ピン配置, 機能
IS62C256
32K x 8 LOW POWER CMOS STATIC RAM
ISSI®
FEATURES
• Access time: 45, 70 ns
• Low active power: 200 mW (typical)
• Low standby power
— 250 µW (typical) CMOS standby
— 28 mW (typical) TTL standby
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V power supply
DESCRIPTION
The ISSI IS62C256 is a low power, 32,768 word by 8-bit
CMOS static RAM. It is fabricated using ISSI's high-
performance, low power CMOS technology.
When CS is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 µW (typical) at CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Select (CS) input and an active LOW Output Enable (OE)
input. The active LOW Write Enable (WE) controls both writing
and reading of the memory.
The IS62C256 is pin compatible with other 32K x 8 SRAMs in
plastic SOP or TSOP (Type I) package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VCC
GND
I/O0-I/O7
DECODER
32K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
CS
CONTROL
OE CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
1

1 Page





IS62C256-45U pdf, ピン配列
IS62C256
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
5V ± 10%
5V ± 10%
DC ELECTRICAL CHARACTERISTICS
Symbol
VOH
VOL
VIH
VIL
ILI
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Test Conditions
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 2.1 mA
GND VIN VCC
ILO Output Leakage
GND VOUT VCC,
Outputs Disabled
Note:
1. VIL = –3.0V for pulse width less than 10 ns.
ISSI®
Com.
Ind.
Com.
Ind.
Min.
2.4
2.2
–0.3
–2
–10
–2
–10
Max.
0.4
VCC + 0.5
0.8
2
10
2
10
Unit
V
V
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol
ICC1
ICC2
ISB1
ISB2
Parameter
Vcc Operating
Supply Current
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
VCC = Max., CS = VIL
IOUT = 0 mA, f = 0
VCC = Max., CS = VIL
IOUT = 0 mA, f = fMAX
VCC = Max.,
VIN = VIH or VIL
CS VIH, f = 0
VCC = Max.,
CS VCC – 0.2V,
VIN VCC – 0.2V, or
VIN 0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
-45 ns
Min. Max.
— 60
— 70
— 70
— 80
—5
— 10
-70 ns
Min. Max.
— 60
— 70
— 65
— 75
—5
— 10
Unit
mA
mA
mA
Com. — 0.5
Ind. — 1.0
— 0.5
— 1.0
mA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
8
10
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
3


3Pages


IS62C256-45U 電子部品, 半導体
IS62C256
ISSI®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter
tWC Write Cycle Time
tSCS CS to Write End
tAW Address Setup Time to Write End
tHA Address Hold from Write End
tSA Address Setup Time
WEtPWE(4)
Pulse Width
tSD Data Setup to Write End
tHD Data Hold from Write End
-45 ns
Min. Max.
45 —
35 —
25 —
0—
0—
25 —
20 —
0—
-70ns
Min. Max.
70 —
60 —
60 —
0—
0—
55 —
30 —
0—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS Controlled, OE is HIGH or LOW) (1 )
t WC
ADDRESS
CS
WE
DOUT
DIN
VALID ADDRESS
t SA t SCS t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD t HD
DATAIN VALID
CS_WR1.eps
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99

6 Page



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