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IS62C1024L-70Q の電気的特性と機能

IS62C1024L-70QのメーカーはIntegrated Silicon Solution Incです、この部品の機能は「128K x 8 LOW POWER CMOS STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS62C1024L-70Q
部品説明 128K x 8 LOW POWER CMOS STATIC RAM
メーカ Integrated Silicon Solution Inc
ロゴ Integrated Silicon Solution  Inc ロゴ 




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IS62C1024L-70Q Datasheet, IS62C1024L-70Q PDF,ピン配置, 機能
IS62C1024L
128K x 8 LOW POWER CMOS STATIC RAM
ISSI®
DECEMBER 2003
FEATURES
• High-speed access time: 35, 70 ns
Low active power: 450 mW (typical)
Low standby power: 150 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
DESCRIPTION
The ISSI IS62C1024L is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write
Enable (WE) controls both writing and reading of the
memory.
The IS62C1024L is available in 32-pin plastic SOP and
TSOP (type 1) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
VDD
GND
I/O0-I/O7
DECODER
128K x 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
CE1
CE2 CONTROL
OE CIRCUIT
WE
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
1

1 Page





IS62C1024L-70Q pdf, ピン配列
IS62C1024L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
ISSI ®
CAPACITANCE(1,2)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage(1)
ILI Input Leakage
Test Conditions
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 2.1 mA
GND VIN VDD
ILO Output Leakage
GND VOUT VDD
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
Com.
Ind.
Com.
Ind.
Min.
2.4
2.2
–0.3
–2
–10
–2
–10
Max.
0.4
VDD + 0.5
0.8
2
10
2
10
Unit
V
V
V
V
µA
µA
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
3


3Pages


IS62C1024L-70Q 電子部品, 半導体
IS62C1024L
ISSI ®
READ CYCLE NO. 2(1,3)
ADDRESS
OE
CE1
CE2
DOUT
tRC
tAA
tDOE
tLZOE
tACE1/tACE2
tLZCE1/
tLZCE2
HIGH-Z
tOHA
tHZOE
tHZCE
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)
Symbol
tWC
tSCE1
tSCE2
tAW
tHA
tSA
tPWE(4)
tSD
tHD
tHZWE(2)
tLZWE(2)
Parameter
Write Cycle Time
CE1 to Write End
CE2 to Write End
Address Setup Time to Write End
Address Hold from Write End
AddressSetupTime
WEPulseWidth
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-35
Min. Max.
35 —
25 —
25 —
25 —
0—
0—
25 —
20 —
0—
— 10
3—
-70
Min. Max.
70 —
60 —
60 —
60 —
0—
0—
50 —
30 —
0—
— 25
5—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03

6 Page



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共有リンク

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