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PDF IS61SPD25632T Data sheet ( Hoja de datos )
| Número de pieza | IS61SPD25632T | |
| Descripción | 256K x 32/ 256K x 36/ 512K x 18 SYNCHRONOUS PIPELINE/ DOUBLE-CYCLE DESELECT STATIC RAM | |
| Fabricantes | Integrated Silicon Solution Inc | |
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IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
ISSIIS61SPD51218T/D IS61LPD51218T/D
®
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINE,
PRELIMINARY INFORMATION
DOUBLE-CYCLE DESELECT STATIC RAM
SEPTEMBER 2000
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enable option for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
• 3.3V I/O For SPD
• 2.5V I/O For LPD
• Double cycle deselect
• Snooze MODE for reduced-power standby
• T version (three chip selects)
• D version (two chip selects)
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
*This speed available only in SPD version
-166*
3.5
6
166
DESCRIPTION
The ISSI IS61SPD25632,IS61SPD25636,S61SPD51218,
IS61LPD25632, IS61LPD25636, and IS61LPD51218 are
high-speed, low-power synchronous static RAMs designed
to provide a burstable, high-performance, secondary cache for
the Pentium™, 680X0™, and PowerPC™ microprocessors.
The IS61SPD25632 and IS61LPD25632 are organized as
262,144 words by 32 bits and the IS61SPD25636 and
IS61LPD25636 are organized as 262,144 words by 36 bits.
The IS61SPD51218 and IS61LPS51218 are organized as
524,288 words by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous inputs
pass through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE).input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
-150 -133
-5 Units
3.8 4
5 ns
6.7 7.5 10 ns
150 133 100 MHz
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
1
1 page  
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
ISSI ®
PIN CONFIGURATION
119-pin PBGA (Top View)
1234567
A
VCCQ
A6
A4 ADSP A8
A16 VCCQ
B
NC CE2 A3 ADSC A9 A17 NC
C
NC A7 A2 VCC A12 A15 NC
D
DQc1 DQPc GND NC GND DQPb DQb8
E
DQc2 DQc3 GND CE GND DQb6 DQb7
F
VCCQ DQc4 GND OE GND DQb5 VCCQ
G
DQc5 DQc6
BWc
ADV
BWb DQb4 DQb3
H
DQc7 DQc8 GND GW GND DQb2 DQb1
J
VCCQ VCC NC VCC NC VCC VCCQ
K
DQd1 DQd2 GND CLK GND DQa7 DQa8
L
DQd4 DQd3 BWd NC BWa DQa5 DQa6
M
VCCQ DQd5
GND
BWE
GND DQa4 VCCQ
N
DQd6 DQd7 GND A1 GND DQa3 DQa2
P
DQd8 DQPd GND A0 GND DQPa DQa1
R
NC
A5 MODE VCC NC A13 NC
T
NC
NC A10 A11 A14 NC
ZZ
U
VCCQ NC NC NC NC NC VCCQ
100-Pin TQFP (D Version)
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
256K x 36
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
CE, CE2
OE
DQa-DQd
MODE
VCC
GND
VCCQ
ZZ
DQPa-DQPd
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V or 2.5V
Snooze Enable
Parity Data I/O
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
5
5 Page 
IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
OPERATING RANGE
Range
Commercial
Ambient Temperature
0°C to +70°C
Industrial
–40°C to +85°C
VCC
3.3V, +10%, –5%
3.3V, +10%, –5%
VCCQ
2.375–3.6V
2.375–3.6V
ISSI ®
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage
ILI Input Leakage Current
ILO Output Leakage Current
Test Conditions
IOH = –2.0 mA, VCCQ = 2.5V
IOH = –4.0 mA, VCCQ = 3.3V
IOL = 2.0 mA, VCCQ = 2.5V
IOL = 8.0 mA, VCCQ = 3.3V
VCCQ = 2.5V
VCCQ = 3.3V
VCCQ = 2.5V
VCCQ = 3.3V
GND ≤ VIN ≤ VCCQ(2)
Com.
Ind.
GND ≤ VOUT ≤ VCCQ, OE = VIH Com.
Ind.
Min.
1.7
2.4
—
—
1.7
2.0
–0.3
–0.3
–2
–5
–2
–5
Max.
—
—
0.7
0.4
VCCQ + 0.3
VCCQ + 0.3
0.7
0.8
2
5
2
5
Unit
V
V
V
V
V
V
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
-166* -150 -133 -100
Max. Max. Max. Max.
ICC AC Operating
Device Selected,
Com. 400
370
350
300
Supply Current
All Inputs = VIL or VIH
Ind. —
400
380
330
OE = VIH, Vcc = Max.
Cycle Time ≥ tKC min.
ISB Standby Current Device Deselected,
Com. 110
VCC = Max.,
Ind. —
All Inputs = VIH or VIL
CLK Cycle Time ≥ tKC min.
105
110
90
95
80
85
*This speed available only in SPD version
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCC.
2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to - GND + 0.2V
or ≥ Vcc – 0.2V.
Unit
mA
mA
mA
mA
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
04/17/01
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet IS61SPD25632T.PDF ] | |
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