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IS61SP6464 の電気的特性と機能

IS61SP6464のメーカーはIntegrated Silicon Solution Incです、この部品の機能は「64K x 64 SYNCHRONOUS PIPELINE STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61SP6464
部品説明 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
メーカ Integrated Silicon Solution Inc
ロゴ Integrated Silicon Solution  Inc ロゴ 




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IS61SP6464 Datasheet, IS61SP6464 PDF,ピン配置, 機能
IS61SP6464
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
ISSI ®
JANUARY 2004
FEATURES
• Fast access time:
– 117, 100 MHz
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Five chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 128-Pin TQFP 14mm x 20mm
package
• Single +3.3V power supply
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VDDQ to alter their power-up state
DESCRIPTION
The ISSI IS61SP6464 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-performance,
secondary cache for the i486™, Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 65,536 words
by 64 bits, fabricated with ISSI's advanced CMOS technology.
The device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. BW1
controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 controls I/
O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-I/
O56, BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP6464 and controlled by the ADV (burst address
advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates after
the wake-up period. A LOW input, i.e., GNDQ, on MODE pin
selects LINEAR Burst. A VDDQ (or no connect) on MODE pin
selects INTERLEAVED Burst.
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
1

1 Page





IS61SP6464 pdf, ピン配列
IS61SP6464
PIN CONFIGURATION
128-Pin TQFP/PQFP
GNDQ
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
VDDQ
GNDQ
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
VDDQ
GNDQ
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ISSI®
102 VDDQ
101 I/O32
100 I/O31
99 I/O30
98 I/O29
97 I/O28
96 I/O27
95 I/O26
94 I/O25
93 I/O24
92 I/O23
91 I/O22
90 GNDQ
89 VDDQ
88 I/O21
87 I/O20
86 I/O19
85 I/O18
84 I/O17
83 I/O16
82 I/O15
81 I/O14
80 I/O13
79 I/O12
78 GNDQ
77 VDDQ
76 I/O11
75 I/O10
74 I/O9
73 I/O8
72 I/O7
71 I/O6
70 I/O5
69 I/O4
68 I/O3
67 I/O2
66 I/O1
65 GNDQ
PIN DESCRIPTIONS
A0-A15
Address Inputs
CLK
ADSP
ADSC
ADV
BW1-BW8
BWE
GW
CE, CE2, CE2,
CE3, CE3
OE
Clock
Processor Address Status
Controller Address Status
Burst Address Advance
Synchronous Byte Write Enable
Byte Write Enable
Global Write Enable
Synchronous Chip Enable
Output Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
I/O1-I/O64
ZZ
MODE
VDD
GND
VDDQ
NC
GNDQ
Data Input/Output
Sleep Mode
Burst Sequence Mode
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V
No Connect
Isolated Output Buffer Ground
3


3Pages


IS61SP6464 電子部品, 半導体
IS61SP6464
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
PD
IOUT
VIN, VOUT
VIN
Parameter
Power Dissipation
Output Current (per I/O)
Voltage Relative to GND for I/O Pins
Voltage Relative to GND for
for Address and Control Inputs
Value
1.0
100
–0.5 to VDDQ + 0.3
–0.5 to 5.5
Unit
W
mA
V
V
VDD Voltage on VDD Supply Relative to GND –0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VDD
3.3V +10%, –5%
3.3V +10%, –5%
ISSI®
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04

6 Page



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共有リンク

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部品番号部品説明メーカ
IS61SP6464

64K x 64 SYNCHRONOUS PIPELINE STATIC RAM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc


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