DataSheet.jp

IS61SP25618-5B PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 IS61SP25618-5B
部品説明 256K x 16/ 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM
メーカ Integrated Silicon Solution Inc
ロゴ Integrated Silicon Solution  Inc ロゴ 



Total 15 pages
		

No Preview Available !

IS61SP25618-5B Datasheet, IS61SP25618-5B PDF,ピン配置, 機能
IS61SP25616
IS61SP25618
256K x 16, 256K x 18 SYNCHRONOUS
PIPELINED STATIC RAM
ISSI®
APRIL 2001
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, -5% power supply
• Power-down snooze mode
DESCRIPTION
The ISSI IS61SP25616 and IS61SP25618 is a high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 262,144
words by 16 bits and 18 bits, fabricated with ISSI's
advanced CMOS technology. The device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned
by BWE being LOW. A LOW on GW input would cause all
bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
-166
3.5
6
166
-150 -133
3.8 4
6.7 7.5
150 133
-5 Units
5 ns
10 ns
100 MHz
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
1

1 Page





ページ 合計 : 15 ページ
PDF
ダウンロード
[ IS61SP25618-5B.PDF ]

共有リンク

Link :

おすすめデータシート

部品番号部品説明メーカ
IS61SP25618-5B

256K x 16/ 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS61SP25618-5TQ

256K x 16/ 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS61SP25618-5TQI

256K x 16/ 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc

www.DataSheet.jp    |   2019   |  メール    |   最新    |   Sitemap