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PDF IS61SF6432-10TQ Data sheet ( Hoja de datos )
| Número de pieza | IS61SF6432-10TQ | |
| Descripción | 64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM | |
| Fabricantes | Integrated Circuit Solution Inc | |
| Logotipo |  |
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IISS616S1F6S43F2 6432
64K x 32 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
FEATURES
• Fast access time: 9 ns, 10 ns
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin LQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention.
• Control pins mode upon power-up:
– FT in pipeline mode
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
• Industrial temperature available
DESCRIPTION
The ICSI IS61SF6432 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 65,536 words
by 32 bits, fabricated with ICSI's advanced CMOS technology.
The device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned
by BWE being LOW. A LOW on GW input would cause all bytes
to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SF6432 and controlled by the ADV (burst address
advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ
(or no connect) on MODE pin selects INTERLEAVED Burst.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SSR004-0B
1
1 page  
IS61SF6432
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
A1’, A0’ = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
TBIAS Temperature Under Bias
–10 to +85
°C
TSTG
Storage Temperature
–55 to +150 °C
PD Power Dissipation
1.8 W
IOUT Output Current (per I/O)
100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins
–0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for
–0.5 to 5.5
V
for Address and Control Inputs
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Circuit Solution Inc.
SSR004-0B
5
5 Page 
IS61SF6432
WRITE CYCLE TIMING: PIPELINE
CLK
ADSP
ADSC
ADV
A15-A0
GW
BWE
BW4-BW1
CE1
CE2
CE3
tKC
tKH
tSS tSH
tKL
ADV must be inactive for ADSP Write tAVS
tAS tAH
WR1
tWS
WR2
tWH
ADSP is blocked by CE1 inactive
ADSC initiate Write
tAVH
WR3
tWS tWH
tWS tWH
WR1
tWS tWH
WR2
tCES tCEH
CE1 Masks ADSP
WR3
tCES tCEH
CE2 and CE3 only sampled with ADSP or ADSC
tCES tCEH
Unselected with CE2
OE
DATAOUT
DATAIN
High-Z
tDS tDH BW4-BW1 only are applied to first cycle of WR2
High-Z 1a
2a 2b 2c 2d
3a
Single Write
Burst Write
Write Unselected
Integrated Circuit Solution Inc.
SSR004-0B
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet IS61SF6432-10TQ.PDF ] | |
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