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IS61SF6432-10PQ の電気的特性と機能

IS61SF6432-10PQのメーカーはIntegrated Circuit Solution Incです、この部品の機能は「64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61SF6432-10PQ
部品説明 64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM
メーカ Integrated Circuit Solution Inc
ロゴ Integrated Circuit Solution Inc ロゴ 




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IS61SF6432-10PQ Datasheet, IS61SF6432-10PQ PDF,ピン配置, 機能
IISS616S1F6S43F2 6432
64K x 32 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
FEATURES
• Fast access time: 9 ns, 10 ns
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin LQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention.
• Control pins mode upon power-up:
– FT in pipeline mode
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
• Industrial temperature available
DESCRIPTION
The ICSI IS61SF6432 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 65,536 words
by 32 bits, fabricated with ICSI's advanced CMOS technology.
The device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned
by BWE being LOW. A LOW on GW input would cause all bytes
to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SF6432 and controlled by the ADV (burst address
advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ
(or no connect) on MODE pin selects INTERLEAVED Burst.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SSR004-0B
1

1 Page





IS61SF6432-10PQ pdf, ピン配列
IS61SF6432
PIN CONFIGURATION
100-Pin LQFP and PQFP (Top View)
NC
DQ17
DQ18
VCCQ
GNDQ
DQ19
DQ20
DQ21
DQ22
GNDQ
VCCQ
DQ23
DQ24
GNDQ
VCC
NC
GND
DQ25
DQ26
VCCQ
GNDQ
DQ27
DQ28
DQ29
DQ30
GNDQ
VCCQ
DQ31
DQ32
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQ16
DQ15
VCCQ
GNDQ
DQ14
DQ13
DQ12
DQ11
GNDQ
VCCQ
DQ10
DQ9
GND
NC
VCC
ZZ
DQ8
DQ7
VCCQ
GNDQ
DQ6
DQ5
DQ4
DQ3
GNDQ
VCCQ
DQ2
DQ1
NC
PIN DESCRIPTIONS
A0-A15
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
GW
CE1, CE2, CE3
OE
Address Inputs
Clock
Processor Address Status
Controller Address Status
Burst Address Advance
Synchronous Byte Write Enable
Byte Write Enable
Global Write Enable
Synchronous Chip Enable
Output Enable
DQ1-DQ32
ZZ
MODE
VCC
GND
VCCQ
GNDQ
NC
Data Input/Output
Sleep Mode
Burst Sequence Mode
+3.3V Power Supply
Ground
Isolated Output Buffer Supply:
+3.3V
Isolated Output Buffer Ground
No Connect
Integrated Circuit Solution Inc.
SSR004-0B
3


3Pages


IS61SF6432-10PQ 電子部品, 半導体
IS61SF6432
OPERATING RANGE
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
VCC
3.3V +10%, –5%
3.3V +10%, –5%
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
VOH Output HIGH Voltage
IOH = –5.0 mA
VOL Output LOW Voltage
IOL = 5.0 mA
VIH Input HIGH Voltage
VIL Input LOW Voltage
ILI Input Leakage Current
GND VIN VCCQ(2)
ILO Output Leakage Current GND VOUT VCCQ, OE = VIH
Min. Max. Unit
2.4 —
V
— 0.4
V
2.0 VCCQ + 0.3 V
–0.3 0.8
V
Com. –5
Ind. –10
5
10
µA
Com. –5
Ind. –10
5
10
µA
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
-9
Min. Typ. Max.
-10
Min. Typ. Max.
Unit
ICC AC Operating
Device Selected,
Com.
Supply Current
All Inputs = VIL or VIH Ind.
OE = VIH, Cycle Time tKC min.
— 300 —
— ——
— 290 —
— 300 —
mA
ISB Standby Current Device Deselected, Com.
VCC = Max.,
Ind.
All Inputs = VIH or VIL
CLK Cycle Time tKC min.
— 60 —
— ——
— 60 —
— 70 —
mA
IZZ Power-Down Mode ZZ = VCCQ,
Com.
Current
CLK Running
Ind.
All Inputs GND + 0.2V
or VCC – 0.2V
— 10 —
— ——
— 10 —
— 20 —
mA
Note:
1. MODE pin has an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect, tied to GND, or tied to
VCCQ.
2. MODE pin should be tied to Vcc or GND. They exhibit ±30 µA maximum leakage current when tied to GND + 0.2V or
Vcc – 0.2V.
6 Integrated Circuit Solution Inc.
SSR004-0B

6 Page



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部品番号部品説明メーカ
IS61SF6432-10PQ

64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM

Integrated Circuit Solution Inc
Integrated Circuit Solution Inc
IS61SF6432-10PQI

64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM

Integrated Circuit Solution Inc
Integrated Circuit Solution Inc


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