DataSheet.jp

IS61S6432-8PQ の電気的特性と機能

IS61S6432-8PQのメーカーはIntegrated Silicon Solution Incです、この部品の機能は「64K x 32 SYNCHRONOUS PIPELINE STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61S6432-8PQ
部品説明 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
メーカ Integrated Silicon Solution Inc
ロゴ Integrated Silicon Solution  Inc ロゴ 




このページの下部にプレビューとIS61S6432-8PQダウンロード(pdfファイル)リンクがあります。
Total 19 pages

No Preview Available !

IS61S6432-8PQ Datasheet, IS61S6432-8PQ PDF,ピン配置, 機能
IS61S6432
ISSI®
64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM
JUNE 2001
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
• Industrial temperature available
DESCRIPTION
The ISSI IS61S6432 is a high-speed, low-power
synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 32 bits, fabricated with ISSI's advanced
CMOS technology. The device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32,
conditioned by BWE being LOW. A LOW on GW input would
cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61S6432 and controlled by the ADV
(burst address advance) input pin.
Asynchronous signals include output enable (OE), sleep
mode input (ZZ), clock (CLK) and burst mode input (MODE).
A HIGH input on the ZZ pin puts the SRAM in the power-
down state. When ZZ is pulled LOW (or no connect), the
SRAM normally operates after three cycles of the wake-up
period. A LOW input, i.e., GNDQ, on MODE pin selects
LINEAR Burst. A VCCQ (or no connect) on MODE pin selects
INTERLEAVED Burst.
FAST ACCESS TIME
Symbol Parameter
-200(1)
tKQ CLK Access Time 4
tKC Cycle Time
5
— Frequency
200
Note:
1. ADVANCE INFORMATION ONLY.
-166
5
6
166
-133
5
7.5
133
-117
5
8.5
117
-5
5
10
100
-6
6
12
83
-7 -8 Unit
7 8 ns
13 15 ns
75 66 MHz
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev. B
06/28/01
1

1 Page





IS61S6432-8PQ pdf, ピン配列
IS61S6432
PIN CONFIGURATION
100-Pin TQFP and PQFP (Top View)
NC
DQ17
DQ18
VCCQ
GNDQ
DQ19
DQ20
DQ21
DQ22
GNDQ
VCCQ
DQ23
DQ24
VCCQ
VCC
NC
GND
DQ25
DQ26
VCCQ
GNDQ
DQ27
DQ28
DQ29
DQ30
GNDQ
VCCQ
DQ31
DQ32
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQ16
DQ15
VCCQ
GNDQ
DQ14
DQ13
DQ12
DQ11
GNDQ
VCCQ
DQ10
DQ9
GND
NC
VCC
ZZ
DQ8
DQ7
VCCQ
GNDQ
DQ6
DQ5
DQ4
DQ3
GNDQ
VCCQ
DQ2
DQ1
NC
ISSI ®
PIN DESCRIPTIONS
A0-A15
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
GW
CE1, CE2, CE3
Address Inputs
Clock
Processor Address Status
Controller Address Status
Burst Address Advance
Synchronous Byte Write Enable
Byte Write Enable
Global Write Enable
Synchronous Chip Enable
OE
DQ1-DQ32
ZZ
MODE
VCC
GND
VCCQ
GNDQ
NC
Output Enable
Data Input/Output
Sleep Mode
Burst Sequence Mode
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V
Isolated Output Buffer Ground
No Connect
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev.B
06/28/01
3


3Pages


IS61S6432-8PQ 電子部品, 半導体
IS61S6432
ISSI ®
DC ELECTRICAL CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
VOH Output HIGH Voltage
IOH = 5.0 mA
2.4
VOL Output LOW Voltage
IOL = 5.0 mA
0.4
VIH Input HIGH Voltage
2.0 VCCQ + 0.3
VIL Input LOW Voltage
0.3 0.8
ILI Input Leakage Current
GND - VIN - VCCQ(2)
Com. 5
Ind. 10
5
10
ILO
Output Leakage Current
GND - VOUT - VCCQ, OE = VIH
Com. 5
5
Ind. 10
10
Notes:
1. MODE pin have an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect,
tied to GND,or tied to VCCQ.
2. MODE pin should be tied to Vcc or GND. They exhibit ±30 µA maximum leakage current when tied
to - GND + 0.2V or Vcc 0.2V.
Unit
V
V
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS (Operating Range)
Symbol Parameter
Test Conditions
-200(1)
Min. Max.
ICC AC Operating Device Selected,
Com. 400
Supply Current All Inputs = VIL or VIH
Ind. — —
OE = VIH, Cycle Time tKC min.
ISB Standby Current Device Deselected,
Com. 100
VCC = Max.,
Ind. — —
CLK Cycle Time tKC min.
IZZ Power-Down ZZ = VCCQ, CLK Running Com. 5
Mode Current All Inputs - GND + 0.2V
Ind. — —
or VCC 0.2V
Note:
1. ADVANCE INFORMATION ONLY.
-166
Min. Max.
215
——
70
——
5
——
-133
Min. Max.
205
——
60
——
5
——
-117
Min. Max. Unit
195 mA
205
50 mA
60
5 mA
10
Symbol Parameter
Test Conditions
-5
Min. Max.
ICC AC Operating Device Selected,
Com. 175
Supply Current All Inputs = VIL or VIH
Ind. 185
OE = VIH, Cycle Time tKC min.
ISB Standby Current Device Deselected,
Com. 25
VCC = Max.,
Ind. 35
CLK Cycle Time tKC min.
IZZ Power-Down ZZ = VCCQ, CLK Running Com. 5
Mode Current All Inputs - GND + 0.2V
Ind. 10
or VCC 0.2V
-6
Min. Max.
165
175
25
35
5
10
-7
Min. Max.
150
160
25
35
5
10
-8
Min. Max. Unit
140 mA
150
25 mA
35
5 mA
10
PB Integrated Silicon Solution, Inc. 1-800-379-4774
Rev.B
06/28/01

6 Page



ページ 合計 : 19 ページ
 
PDF
ダウンロード
[ IS61S6432-8PQ データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
IS61S6432-8PQ

64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS61S6432-8PQI

64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap