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PDF IS61S6432-6TQI Data sheet ( Hoja de datos )
| Número de pieza | IS61S6432-6TQI | |
| Descripción | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM | |
| Fabricantes | Integrated Silicon Solution Inc | |
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IS61S6432
ISSI®
64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM
JUNE 2001
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• Single +3.3V power supply
• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
• Industrial temperature available
DESCRIPTION
The ISSI IS61S6432 is a high-speed, low-power
synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 32 bits, fabricated with ISSI's advanced
CMOS technology. The device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32,
conditioned by BWE being LOW. A LOW on GW input would
cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61S6432 and controlled by the ADV
(burst address advance) input pin.
Asynchronous signals include output enable (OE), sleep
mode input (ZZ), clock (CLK) and burst mode input (MODE).
A HIGH input on the ZZ pin puts the SRAM in the power-
down state. When ZZ is pulled LOW (or no connect), the
SRAM normally operates after three cycles of the wake-up
period. A LOW input, i.e., GNDQ, on MODE pin selects
LINEAR Burst. A VCCQ (or no connect) on MODE pin selects
INTERLEAVED Burst.
FAST ACCESS TIME
Symbol Parameter
-200(1)
tKQ CLK Access Time 4
tKC Cycle Time
5
— Frequency
200
Note:
1. ADVANCE INFORMATION ONLY.
-166
5
6
166
-133
5
7.5
133
-117
5
8.5
117
-5
5
10
100
-6
6
12
83
-7 -8 Unit
7 8 ns
13 15 ns
75 66 MHz
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev. B
06/28/01
1
1 page  
IS61S6432
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
ISSI ®
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1,2,3)
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under Bias
–40 to +85
°C
TSTG
Storage Temperature
–55 to +150
°C
PD Power Dissipation
1.8 W
IOUT Output Current (per I/O)
100 mA
VIN, VOUT
Voltage Relative to GND for I/O Pins
–0.5 to VCCQ + 0.3
V
VIN
Voltage Relative to GND for for Address and Control Inputs
–0.5 to 5.5
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V +10%, –5%
3.3V +10%, –5%
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
5
5 Page 
IS61S6432
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
ISSI ®
Symbol
tKC
tKH
tKL
tAS
tSS
tWS
tDS
tCES
tAVS
tAH
tSH
tDH
tWH
tCEH
tAVH
tCFG(2)
Parameter
Cycle Time
Clock High Time
Clock Low Time
Address Setup Time
Address Status Setup Time
Write Setup Time
Data In Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
Address Status Hold Time
Data In Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Configuration Setup
-200(1)
Min. Max.
5—
1.6 —
1.6 —
2—
2—
2—
2—
2—
2—
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
25 —
-166
Min. Max.
6—
2.4 —
2.4 —
2.5 —
2.5 —
2.5 —
2.5 —
2.5 —
2.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
25 —
-133
-117
Min. Max. Min. Max.
7.5 — 8.5 —
2.8 — 3 —
2.8 — 3 —
2.5 — 2.5 —
2.5 — 2.5 —
2.5 — 2.5 —
2.5 — 2.5 —
2.5 — 2.5 —
2.5 — 2.5 —
0.5 — 0.5 —
0.5 — 0.5 —
0.5 — 0.5 —
0.5 — 0.5 —
0.5 — 0.5 —
0.5 — 0.5 —
30 — 35 —
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol Parameter
-5 -6
Min. Max. Min. Max.
tKC Cycle Time
10 — 12 —
tKH Clock High Time
3.5 — 4 —
tKL Clock Low Time
3.5 — 4 —
tAS Address Setup Time
2.5 — 2.5 —
tSS Address Status Setup Time 2.5 — 2.5 —
tWS Write Setup Time
2.5 — 2.5 —
tDS Data In Setup Time
2.5 — 2.5 —
tCES Chip Enable Setup Time
2.5 — 2.5 —
tAVS
Address Advance Setup Time
2.5 — 2.5 —
tAH Address Hold Time
0.5 — 0.5 —
tSH Address Status Hold Time
0.5 — 0.5 —
tDH Data In Hold Time
0.5 — 0.5 —
tWH Write Hold Time
0.5 — 0.5 —
tCEH Chip Enable Hold Time
0.5 — 0.5 —
tAVH Address Advance Hold Time 0.5 — 0.5 —
tCFG(2)
Configuration Setup
35 — 45 —
Note:
1. ADVANCE INFORMATION ONLY.
2. Configuration signal MODE is static and must not change during normal operation.
-7 -8
Min. Max. Min. Max.
13 — 15 —
6—6—
6—6—
2.5 — 2.5 —
2.5 — 2.5 —
2.5 — 2.5 —
2.5 — 2.5 —
2.5 — 2.5 —
2.5 — 2.5 —
0.5 — 0.5 —
0.5 — 0.5 —
0.5 — 0.5 —
0.5 — 0.5 —
0.5 — 0.5 —
0.5 — 0.5 —
52 — 60 —
Integrated Silicon Solution, Inc. • 1-800-379-4774
Rev.B
06/28/01
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet IS61S6432-6TQI.PDF ] | |
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