PDF IS61NP25636-133BI Data sheet ( Hoja de datos )

Número de pieza	IS61NP25636-133BI
Descripción	256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM
Fabricantes	Integrated Silicon Solution Inc
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IS61NP25632 IS61NP25636 IS61NP51218 ISSIIS61NLP25632 IS61NLP25636 IS61NLP51218 ® 256K x 32, 256K x 36 and 512K x 18 PRELIMINARY INFORMATION PIPELINE 'NO WAIT' STATE BUS SRAM APRIL 2001 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining for TQFP • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 119 PBGA package • Single +3.3V power supply (± 5%) • NP Version: 3.3V I/O Supply Voltage • NLP Version: 2.5V I/O Supply Voltage • Industrial temperature available DESCRIPTION The 8 Meg 'NP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. They are organized as 262,144 words by 32 bits, 262,144 words by 36 bits and 524,288 words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -133 4.2 7.5 133 -100 Units 5 ns 10 ns 100 MHz This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00E 04/26/01 1 1 page IS61NP25632 IS61NP25636 IS61NP51218 IS61NLP25632 IS61NLP25636 IS61NLP51218 ISSI ® PIN CONFIGURATION 119-pin PBGA (Top View) and 100-Pin TQFP 1234567 A VCCQ A6 A4 NC B NC CE2 A3 ADV C NC A7 A2 VCC D DQ9 NC GND NC E NC DQ10 GND CE F VCCQ NC GND OE G NC DQ11 BWb A17 H DQ12 NC GND WE J VCCQ VCC NC VCC K NC DQ13 GND CLK L DQ14 NC NC NC M VCCQ DQ15 GND CKE N DQ16 NC GND A1 P NC DQP2 GND A0 R NC A5 MODE VCC T NC A10 A11 NC U VCCQ NC NC NC A8 A16 VCCQ A9 CE2 NC A12 A15 NC GND DQP1 NC GND NC DQ8 GND DQ7 VCCQ NC NC DQ6 GND DQ5 NC NC VCC VCCQ GND BWa NC DQ3 DQ4 NC GND NC VCCQ GND DQ2 NC GND NC DQ1 VCC A13 NC A14 A18 ZZ NC NC VCCQ NC NC NC VCCQ GND NC NC DQ9 DQ10 GND VCCQ DQ11 DQ12 VCC VCC VCC GND DQ13 DQ14 VCCQ GND DQ15 DQ16 DQP2 NC GND VCCQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A10 NC NC VCCQ GND NC DQP1 DQ8 DQ7 GND VCCQ DQ6 DQ5 GND VCC VCC ZZ DQ4 DQ3 VCCQ GND DQ2 DQ1 NC NC GND VCCQ NC NC NC 512K x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A2-A18 Synchronous Address Inputs CLK Synchronous Clock ADV BWa-BWb WE CKE Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQ1-DQ16 Synchronous Data Input/Output MODE Burst Sequence Mode Selection VCC +3.3V Power Supply GND Ground VCCQ Isolated Output Buffer Supply: +3.3V/2.5V ZZ Snooze Enable DQP1-DQP2 Parity Data I/O DQP1 is parity for DQ1-8; DQP2 is parity for DQ9-16 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00E 04/26/01 5 5 Page IS61NP25632 IS61NP25636 IS61NP51218 IS61NLP25632 IS61NLP25636 IS61NLP51218 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 ISSI ® 2.5V I/O OUTPUT LOAD EQUIVALENT OUTPUT ZO = 50Ω 50Ω 1.25V +2.5V 1,667 Ω OUTPUT 1,538 Ω 5 pF Including jig and scope Figure 3 Figure 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00E 04/26/01 11 11 Page

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Número de pieza	Descripción	Fabricantes
IS61NP25636-133B	256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM	Integrated Silicon Solution Inc
IS61NP25636-133BI	256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM	Integrated Silicon Solution Inc

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