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IS61NLF25636 の電気的特性と機能

IS61NLF25636のメーカーはIntegrated Silicon Solution Incです、この部品の機能は「SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61NLF25636
部品説明 SRAM
メーカ Integrated Silicon Solution Inc
ロゴ Integrated Silicon Solution  Inc ロゴ 




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IS61NLF25636 Datasheet, IS61NLF25636 PDF,ピン配置, 機能
IS61NF25632 IS61NF25636 IS61NF51218
ISSIIS61NLF25632 IS61NLF25636 IS61NLF51218
®
256K x 32, 256K x 36 and 512K x 18
PRELIMINARY INFORMATION
FLOW-THROUGH 'NO WAIT' STATE BUS
APRIL 2001
SRAM
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining for TQFP
• Power Down mode
• Common data inputs and data outputs
CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119 PBGA package
• Single +3.3V power supply (± 5%)
• NF Version: 3.3V I/O Supply Voltage
• NLF Version: 2.5V I/O Supply Voltage
• Industrial temperature available
DESCRIPTION
The 8 Meg 'NF' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 262,144 words by 32 bits, 262,144 words
by 36 bits and 524,288 words by 18 bits, fabricated with
ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
-10 Units
10 ns
12 ns
83 MHz
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
04/26/01
1

1 Page





IS61NLF25636 pdf, ピン配列
IS61NF25632 IS61NF25636 IS61NF51218
IS61NLF25632 IS61NLF25636 IS61NLF51218
ISSI ®
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
1234567
A
VCCQ
A6
A4 NC
B
NC CE2 A3 ADV
C
NC A7 A2 VCC
D
DQc1 NC GND NC
E
DQc2 DQc3 GND
CE
F
VCCQ DQc4 GND
OE
G
DQc5 DQc6 BWc
A17
H
DQc7 DQc8 GND
WE
J
VCCQ VCC NC VCC
K
DQd1 DQd2 GND CLK
L
DQd4 DQd3 BWd
NC
M
VCCQ DQd5
GND
CKE
N
DQd6 DQd7 GND
A1
P
DQd8 NC GND A0
R
NC
A5 MODE VCC
T
NC
NC A10 A11
U
VCCQ NC NC NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
NC
A14
NC
A16
CE2
VCCQ
NC
A15 NC
NC DQb8
DQb6 DQb7
DQb5 VCCQ
DQb4 DQb3
DQb2 DQb1
VCC VCCQ
DQa7 DQa8
DQa5 DQa6
DQa4 VCCQ
DQa3 DQa2
NC DQa1
A13 NC
NC ZZ
NC VCCQ
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
GND
VCC
VCC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
GND
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
256K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17
Synchronous Address Inputs
CLK Synchronous Clock
ADV
BWa-BWd
WE
CKE
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ Snooze Enable
Integrated Silicon Solution, Inc. 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
04/26/01
3


3Pages


IS61NLF25636 電子部品, 半導体
IS61NF25632 IS61NF25636 IS61NF51218
IS61NLF25632 IS61NLF25636 IS61NLF51218
STATE DIAGRAM
ISSI ®
READ
BEGIN
READ
DS
READ
READ
WRITE
DS
WRITE
BEGIN
WRITE
WRITE
READ BURST
BURST
BURST
READ
DESELECT
BURST WRITE
DS BURST
DS
WRITE
DS
READ
BURST
WRITE
BURST
SYNCHRONOUS TRUTH TABLE(1)
Operation
Address
Used
CS1 CS2 CS2 ADV WE BWx OE CKE CLK
Not Selected Continue
N/A
XXXHXXXL
Begin Burst Read
External Address L H L L H X L L
Continue Burst Read
Next Address X X X H X X L L
NOP/Dummy Read
External Address L H L L H X H L
Dummy Read
Next Address X X X H X X H L
Begin Burst Write
External Address L H L L L L X L
Continue Burst Write
Next Address X X X H X L X L
NOP/Write Abort
N/A L H L L L H X L
Write Abort
Next Address X X X H X H X L
Ignore Clock
Current Address X X X X X X X H
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
6 Integrated Silicon Solution, Inc. 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
04/26/01

6 Page



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共有リンク

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部品番号部品説明メーカ
IS61NLF25632

SRAM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS61NLF25636

SRAM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS61NLF25636A

(IS61NVFxxxxxA) STATE BUS SRAM

ISSI
ISSI


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