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IS61LV6416-10KIのメーカーはETCです、この部品の機能は「64K X 16 HIGH SPEED CMOS STATIC RAM WITH 3.3 V SUPPLY」です。 |
部品番号 | IS61LV6416-10KI |
| |
部品説明 | 64K X 16 HIGH SPEED CMOS STATIC RAM WITH 3.3 V SUPPLY | ||
メーカ | ETC | ||
ロゴ | |||
このページの下部にプレビューとIS61LV6416-10KIダウンロード(pdfファイル)リンクがあります。 Total 8 pages
IS61LV6416
64K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
FEATURES
High-speed access time: 8, 10, 12, and 15 ns
CMOS low power operation
250 mW (typical) operating
250 µW (typical) standby
TTL compatible interface levels
Single 3.3V power supply
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The 1+51 IS61LV6416 is a high-speed, 1,048,576-bit static
RAM organized as 65,536 words by 16 bits. It is fabricated
using 1+51's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns with low power
consumption.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS61LV6416 is packaged in the JEDEC standard 44-pin
400mil SOJ, 44-pin 400mil TSOP-2, and 48-pin 6*8mm TF-
BGA.
A0-A15
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
64K x 16
MEMORY ARRAY
COLUMN I/O
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR013-0C
1
1 Page IS61LV6416
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
VTERM Terminal Voltage with Respect to GND
TSTG Storage Temperature
PT Power Dissipation
IOUT DC Output Current (LOW)
Value
0.5 to Vcc+0.5
65 to +150
1.5
20
Unit
V
°C
W
mA
Note:
1. Stress greater than those listed under
ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the
device. This is a stress rating only and
functional operation of the device at
these or any other conditions above
those indicated in the operational sec-
tions of this specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods may
affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
40°C to +85°C
Vcc
3.3V ± 10%
3.3V ± 10%
!
"
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
VOH
VOL
VIH
VIL
ILI
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Test Conditions
VCC = Min., IOH = 4.0 mA
VCC = Min., IOL = 8.0 mA
GND ≤ VIN ≤ VCC
ILO Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
Notes:
1. VIL (min.) = 2.0V for pulse width less than 10 ns.
2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
#Min. Max. Unit
2.4 V
$ 0.4 V
2 VCC + 0.3 V
0.3 0.8 V
Com.
Ind.
Com.
Ind.
2
-5
2
-5
%2 µA
5
2 µA
5
&
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol
ICC
ISB
Parameter
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
ISB CMOS Standby
Current (CMOS Inputs)
Test Conditions
VCC = Max.,
IOUT = 0 mA, f = fMAX
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH , f = 0
VCC = Max.,
CE ≥ VCC 0.2V,
VIN ≥ VCC 0.2V, or
VIN ≤ 0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
-8 ns
Min. Max.
220
230
30
40
10
15
-10 ns
Min. Max.
200
210
30
40
10
15
-12 ns
Min. Max.
180
190
30
40
10
15
-15 ns
Min. Max.
180
190
30
40
Unit
mA
mA
10 mA
15
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
'
Integrated Circuit Solution Inc.
SR013-0C
3
3Pages IS61LV6416
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter
tWC Write Cycle Time
tSCE CE to Write End
tAW Address Setup Time
to Write End
tHA Address Hold from Write End
tSA Address Setup Time
tPWB LB, UB Valid to End of Write
tPWE WE Pulse Width
tSD Data Setup to Write End
tHD Data Hold from Write End
tHZWE WE LOW to High-Z Output
tLZWE WE HIGH to Low-Z Output
-8
Min. Max.
8
7
7
0
0
7
7
4.5
0
4
3
-10
Min. Max.
10
8
8
0
0
8
8
5
0
5
3
-12
Min. Max.
12
9
9
0
0
9
9
6
0
6
3
-15
Min. Max.
15
10
10
Unit
ns
ns
ns
0 ns
0 ns
10 ns
10 ns
7 ns
0 ns
7 ns
3 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
6 Integrated Circuit Solution Inc.
SR013-0C
6 Page | |||
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部品番号 | 部品説明 | メーカ |
IS61LV6416-10K | 64K X 16 HIGH SPEED CMOS STATIC RAM WITH 3.3 V SUPPLY | ETC |
IS61LV6416-10KI | 64K X 16 HIGH SPEED CMOS STATIC RAM WITH 3.3 V SUPPLY | ETC |