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PDF IS61LV5128-10K Data sheet ( Hoja de datos )
| Número de pieza | IS61LV5128-10K | |
| Descripción | 512K x 8 HIGH-SPEED CMOS STATIC RAM | |
| Fabricantes | Integrated Silicon Solution Inc | |
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IS61LV5128
ISSI®
512K x 8 HIGH-SPEED CMOS STATIC RAM
JULY 2001
FEATURES
• High-speed access times:
10, 12 and 15 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
• CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 36-pin 400-mil SOJ
– 36-pin miniBGA
– 44-pin TSOP (Type II)
DESCRIPTION
The ISSI IS61LV5128 is a very high-speed, low power,
524,288-word by 8-bit CMOS static RAM. The IS61LV5128
is fabricated using ISSI's high-performance CMOS tech-
nology. This highly reliable process coupled with innova-
tive circuit design techniques, yields higher performance
and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS61LV5128 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
The IS61LV5128 is available in 36-pin 400-mil SOJ, 36-
pin mini BGA, and 44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
VCC
GND
I/O0-I/O7
DECODER
512K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
CE
CONTROL
OE CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
1
1 page  
IS61LV5128
ISSI ®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
Unit
tRC Read Cycle Time
10 —
12 —
15 —
ns
tAA
Address Access Time
— 10
— 12
— 15
ns
tOHA Output Hold Time
3—
3—
3—
ns
tACE CE Access Time
— 10
— 12
— 15
ns
tDOE OE Access Time
—4
—5
—7
ns
tLZOE(2)
OE to Low-Z Output
0—
0—
0—
ns
tHZOE(2)
OE to High-Z Output
04
05
06
ns
tLZCE(2)
CE to Low-Z Output
3—
3—
3—
ns
tHZCE(2)
CE to High-Z Output
04
06
08
ns
tPU Power Up Time
0—
0—
0—
ns
tPD Power Down Time
— 10
— 12
— 15
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
3.3V
319 Ω
OUTPUT
30 pF
Including
jig and
scope
353 Ω
3.3V
319 Ω
OUTPUT
5 pF
Including
jig and
scope
353 Ω
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/16/01
5
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