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IS61LV256-25N の電気的特性と機能

IS61LV256-25NのメーカーはETCです、この部品の機能は「32K x 8 LOW VOLTAGE CMOS STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61LV256-25N
部品説明 32K x 8 LOW VOLTAGE CMOS STATIC RAM
メーカ ETC
ロゴ ETC ロゴ 




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IS61LV256-25N Datasheet, IS61LV256-25N PDF,ピン配置, 機能
IS61LV256
IS61LV256
32K x 8 LOW VOLTAGE CMOS STATIC RAM
ISSIISSI®®
FEBRUARY 1996
FEATURES
• High-speed access time: 12, 15, 20, 25 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
— 345 mW (max.) operating
— 7 mW (max.) CMOS standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three-state outputs
DESCRIPTION
The ISSI IS61LV256 is a very high-speed, low power,
32,768-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 12 ns maximum.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IS61LV256 is available in the JEDEC standard 28-pin,
300-mil DIP and SOJ, plus the 450-mil TSOP package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
VCC
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
256 X 1024
MEMORY ARRAY
COLUMN I/O
CE
CONTROL
OE CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1996, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
2-1

1 Page





IS61LV256-25N pdf, ピン配列
IS61LV256
ISSI®
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V +10%, –5%
3.3V ± 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage(1)
ILI Input Leakage
ILO Output Leakage
Test Conditions
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 4.0 mA
GND VIN VCC
GND VOUT VCC, Outputs Disabled
Com.
Ind.
Com.
Ind.
Min.
2.4
2.2
–0.3
–2
–5
–2
–5
Max.
0.4
VCC + 0.3
0.8
2
5
2
5
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Unit
V
V
V
V
µA
µA
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
ICC1 Vcc Operating
Supply Current
ICC2 Vcc Dynamic Operating
Supply Current
ISB1 TTL Standby Current
(TTL Inputs)
ISB2 CMOS Standby
Current (CMOS Inputs)
Test Conditions
VCC = Max., CE = VIL
IOUT = 0 mA, f = 0
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX
VCC = Max.,
VIN = VIH or VIL
CE VIH, f = 0
VCC = Max.,
CE VCC – 0.2V,
VIN > VCC – 0.2V, or
VIN 0.2V, f = 0
-12 ns
Min. Max.
Com. — 50
Ind. — —
Com. — 100
Ind. — —
Com. — 10
Ind. — —
Com. — 2
Ind. — —
-15 ns
Min. Max.
— 50
— 60
— 90
— 100
— 10
— 20
—2
—5
-20 ns
Min. Max.
— 50
— 60
— 80
— 90
— 10
— 20
—2
—5
-25 ns
Min. Max.
— 50
— 60
— 70
— 80
— 10
— 20
—2
—5
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Unit
mA
mA
mA
mA
CAPACITANCE(1,2)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
6
5
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61
2-3


3Pages


IS61LV256-25N 電子部品, 半導体
IS61LV256
ISSI®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter
tWC Write Cycle Time
tSCE CE to Write End
tAW Address Setup Time to Write End
tHA Address Hold from Write End
tSA Address Setup Time
WEtPWE(4)
Pulse Width
tSD Data Setup to Write End
tHD
tHZWE(2)
tLZWE(2)
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-12 ns
Min. Max.
12 —
8—
8—
0—
0—
8—
6—
0—
—6
0—
-15 ns
Min. Max.
15 —
10 —
10 —
0—
0—
10 —
8—
0—
—7
0—
-20 ns
Min. Max.
20 —
13 —
15 —
0—
0—
13 —
10 —
0—
—8
0—
-25 ns
Min. Max.
25 —
15 —
20 —
0—
0—
15 —
12 —
0—
— 10
0—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
ADDRESS
CE
WE
DOUT
DIN
tWC
tSCE
tHA
tAW
tPWE
tSA tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD tHD
DATA-IN VALID
2-6 Integrated Silicon Solution, Inc.
Rev. F 0296
SR81995LV61

6 Page



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共有リンク

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部品番号部品説明メーカ
IS61LV256-25J

32K x 8 LOW VOLTAGE CMOS STATIC RAM

ETC
ETC
IS61LV256-25N

32K x 8 LOW VOLTAGE CMOS STATIC RAM

ETC
ETC
IS61LV256-25T

32K x 8 LOW VOLTAGE CMOS STATIC RAM

ETC
ETC


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