DataSheet.jp

IS42S81600A-10T の電気的特性と機能

IS42S81600A-10TのメーカーはIntegrated Silicon Solution Incです、この部品の機能は「16Meg x 8/ 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS42S81600A-10T
部品説明 16Meg x 8/ 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
メーカ Integrated Silicon Solution Inc
ロゴ Integrated Silicon Solution  Inc ロゴ 




このページの下部にプレビューとIS42S81600A-10Tダウンロード(pdfファイル)リンクがあります。
Total 61 pages

No Preview Available !

IS42S81600A-10T Datasheet, IS42S81600A-10T PDF,ピン配置, 機能
IS42S81600A,
IS42S16800A,
IS42S32400A,
16Meg x 8, 8Meg x16 & 4Meg x 32
128-MBIT SYNCHRONOUS DRAM
ISSI®
PRELIMINARY INFORMATION
JANUARY 2005
FEATURES
• Clock frequency: 166,143,100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
IS42S81600A
VDD VDDQ
3.3V 3.3V
IS42S16800A
3.3V 3.3V
IS42S32400A
3.3V 3.3V
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Industrial Temperature Availability
• Lead-free Availability
OVERVIEW
ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized as follows.
IS42S81600A
4M x8x4 Banks
54-pin TSOPII
IS42S16800A
2M x16x4 Banks
54-pin TSOPII
IS42S32400A
1M x32x4 Banks
86-pin TSOPII
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
-6 -7 -10 Unit
6 7 10 ns
- 10 10 ns
166 143 100 Mhz
- 100 100 Mhz
5.4 5.4 7 ns
- 6 9 ns
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION,Rev. 00C
01/20/05
1

1 Page





IS42S81600A-10T pdf, ピン配列
IS42S81600A, IS42S16800A, IS42S32400A
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
ISSI ®
VDD
I/O0
VDDQ
NC
I/O1
VSSQ
NC
I/O2
VDDQ
NC
I/O3
VSSQ
NC
VDD
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 I/O7
52 VSSQ
51 NC
50 I/O6
49 VDDQ
48 NC
47 I/O5
46 VSSQ
45 NC
44 I/O4
43 VDDQ
42 NC
41 VSS
40 NC
39 DQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
PIN DESCRIPTIONS
A0-A11
A0-A9
BA0, BA1
I/O0 to I/O7
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM
VDD
Vss
VDDQ
VssQ
NC
Write Enable
x 8 Lower Byte, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00C
01/20/05
3


3Pages


IS42S81600A-10T 電子部品, 半導体
IS42S81600A, IS42S16800A, IS42S32400A
ISSI ®
PIN FUNCTIONS
Symbol
A0-A11
Type
Input Pin
BA0, BA1
CAS
CKE
CLK
CS
DQML,
DQMH
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
DQM0-DQM3
DQM
RAS
WE
VDDQ
VDD
VSSQ
VSS
Input Pin
Input Pin
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A9 (x8); A0-A8
(x16); A0-A7(x32) with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command
to determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when CS is HIGH.
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode,DQML and DQMH control the input buffer.
WhenDQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. WhenDQML or DQMH is HIGH, input data is masked and
cannot be written to the device.
For IS42S32400A only
For IS42S81600A only.
RAS, in conjunction with CAS and WE, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Command
Truth Table" item for details on device commands.
VDDQ is the output buffer power supply.
VDD is the device internal power supply.
VSSQ is the output buffer ground.
VSS is the device internal ground.
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
01/20/05

6 Page



ページ 合計 : 61 ページ
 
PDF
ダウンロード
[ IS42S81600A-10T データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
IS42S81600A-10T

16Meg x 8/ 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS42S81600A-10TI

16Meg x 8/ 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS42S81600A-10TL

16Meg x 8/ 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap