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IS41LV16256-35T の電気的特性と機能

IS41LV16256-35TのメーカーはIntegrated Silicon Solution Incです、この部品の機能は「256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS41LV16256-35T
部品説明 256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
メーカ Integrated Silicon Solution Inc
ロゴ Integrated Silicon Solution  Inc ロゴ 




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IS41LV16256-35T Datasheet, IS41LV16256-35T PDF,ピン配置, 機能
IS41C16256
IS41LV16256
256K x 16 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
ISSI®
JUNE 2000
FEATURES
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode : RAS-Only, CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single power supply
5V ± 10% (IS41C16256)
3.3V ± 10% (IS41LV16256)
• Byte Write and Byte Read operation via two CAS
• Extended Temperature Range -30oC to 85oC
• Industrail Temperature Range -40oC to 85oC
DESCRIPTION
The ISSI IS41C16256 and IS41LV16256 are 262,144 x 16-bit
high-performanceCMOSDynamicRandomAccessMemory. Both
products offer accelerated cycle access EDO Page Mode. EDO
Page Mode allows 512 random accesses within a single row with
access cycle time as short as 10ns per 16-bit word. The Byte Write
control, of upper and lower byte, makes the IS41C16256 and
IS41LV16256 ideal for use in 16 and 32-bit wide data bus systems.
These features make the IS41C16256 and IS41LV1626 ideally
suited for high band-width graphics, digital signal processing,
high-performance computing systems, and peripheral applications.
The IS41C16256 and IS41LV16256 are packaged in 40-pin
400-mil SOJ and TSOP (Type II).
KEY TIMING PARAMETERS
Parameter
-35 -50 -60 Unit
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
35 50 60 ns
10 14 15 ns
Max. Column Address Access Time (tAA)
18
25
30
ns
Min. EDO Page Mode Cycle Time (tPC) 12 20 25 ns
Min. Read/Write Cycle Time (tRC)
60 90 110 ns
PIN CONFIGURATIONS
40-Pin TSOP (Type II)
40-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
11
12
13
14
15
16
17
18
19
20
40 GND
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 GND
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 GND
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 GND
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 GND
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 GND
PIN DESCRIPTIONS
A0-A8
I/O0-15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Power
Ground
No Connection
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. J
06/29/00
1

1 Page





IS41LV16256-35T pdf, ピン配列
IS41C16256
IS41LV16256
ISSI ®
TRUTH TABLE
Function
RAS LCAS UCAS WE OE Address tR/tC I/O
Standby
H HHXX
X High-Z
Read: Word
L L L H L ROW/COL DOUT
Read: Lower Byte
L L H H L ROW/COL Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte
L H L H L ROW/COL Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write)
L L L L X ROW/COL DIN
Write: Lower Byte (Early Write)
L
L H L X ROW/COL Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write)
L
H L L X ROW/COL Lower Byte, High-Z
Upper Byte, DIN
Read-Write(1,2)
L L L HL LH ROW/COL DOUT, DIN
EDO Page-Mode Read(2) 1st Cycle:
2nd Cycle:
Any Cycle:
L
L
L
HL HL
HL HL
LH LH
H
H
H
L ROW/COL DOUT
L
NA/COL
DOUT
L
NA/NA
DOUT
EDO Page-Mode Write(1) 1st Cycle: L
2nd Cycle: L
HL HL
HL HL
L
L
X ROW/COL DIN
X NA/COL DIN
EDO Page-Mode
Read-Write(1,2)
1st Cycle: L
2nd Cycle: L
HL HL HL LH ROW/COL
HL HL HL LH NA/COL
DOUT, DIN
DOUT, DIN
Hidden Refresh2)
RAS-Only Refresh
Read LHL L L H L ROW/COL DOUT
Write LHL L L L X ROW/COL DOUT
L H H X X ROW/NA High-Z
CBR Refresh(3)
HL
L
L
X
X
X High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. J
06/29/00
3


3Pages


IS41LV16256-35T 電子部品, 半導体
IS41C16256
IS41LV16256
ISSI ®
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max. Unit
IIL Input Leakage Current
Any input 0V VIN Vcc
Other inputs not under test = 0V
10 10 µA
IIO Output Leakage Current
Output is disabled (Hi-Z)
0V VOUT Vcc
10 10 µA
VOH Output High Voltage Level
IOH = 2.5 mA
2.4
V
VOL Output Low Voltage Level
ICC1 Stand-by Current: TTL
IOL = +2.1 mA
0.4 V
RAS, LCAS, UCAS VIH
Commercial
Industrial
Commercial
Industrial
5V
5V
3V
3V
3 mA
4
2
3
ICC2 Stand-by Current: CMOS
RAS, LCAS, UCAS VCC 0.2V
5V
3V
2 mA
1
ICC3 Operating Current:
RAS, LCAS, UCAS,
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
ICC4 Operating Current:
RAS = VIL, LCAS, UCAS,
EDO Page Mode(2,3,4)
Cycling tPC = tPC (min.)
Average Power Supply Current
ICC5
Refresh Current:
RAS-Only(2,3)
RAS Cycling, LCAS, UCAS VIH
tRC = tRC (min.)
Average Power Supply Current
-35 230 mA
-50 180
-60 170
-35 220 mA
-50 170
-60 160
-35 230 mA
-50 180
-60 170
ICC6 Refresh Current:
RAS, LCAS, UCAS Cycling
CBR(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
-35 230 mA
-50 180
-60 170
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6 Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. J
06/29/00

6 Page



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部品番号部品説明メーカ
IS41LV16256-35K

256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS41LV16256-35T

256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc


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