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IS24C64-2 の電気的特性と機能

IS24C64-2のメーカーはIntegrated Silicon Solution Incです、この部品の機能は「65/536-bit/32/768-bit 2-WIRE SERIAL CMOS EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS24C64-2
部品説明 65/536-bit/32/768-bit 2-WIRE SERIAL CMOS EEPROM
メーカ Integrated Silicon Solution Inc
ロゴ Integrated Silicon Solution  Inc ロゴ 




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IS24C64-2 Datasheet, IS24C64-2 PDF,ピン配置, 機能
IS24C32-2/3
IS24C64-2/3
65,536-bit/32,768-bit 2-WIRE SERIAL
CMOS EEPROM
ISSI®
PRELIMINARY INFORMATION
APRIL 2001
FEATURES
• Low Power CMOS Technology
– Standby Current less than 10 µA (5.5V)
– Read Current (typical) less than 1 mA (5.5V)
– Write Current (typical) less than 3 mA (5.5V)
• Low Voltage Operation
– IS24C64-2 & IS24C32-2: Vcc = 1.8V to 5.5V
– IS24C64-3 & IS24C32-3: Vcc = 2.5V to 5.5V
• 100 KHz (1.8V) and 400 KHz (5V) Compatibility
• Hardware Data Protection
– Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• 8-pin PDIP and 8-pin SOIC packages
• Self time write cycle with auto clear
– 5 ms @ 2.5V
• Organization:
– IS24C64-2 and IS24C64-3: 8192x8
– IS24C32-2 and IS24C32-3: 4096x8
• 32-Byte Page Write Buffer
• Two-Wire Serial Interface
– Bi-directional data transfer protocol
• High Reliability
– Endurance: 1,000,000 Cycles
– Data Retention: 100 Years
• Commercial and Industrial temperature ranges
PRODUCT OFFERING OVERVIEW
Part No
IS24C64-2
IS24C64-3
IS24C32-2
IS24C32-3
Voltage
1.8V-5.5V
2.5V-5.5V
1.8V-5.5V
2.5V-5.5V
Speed
100 KHz
400 KHz
100 KHz
400 KHz
Standby ICC
< 5 µA
< 10 µA
< 5 µA
< 10 µA
Read ICC
1 mA
1 mA
1 mA
1 mA
Write ICC
3 mA
3 mA
3 mA
3 mA
Temperature
C,I
C,I
C,I
C,I
DESCRIPTION
The IS24C64-2 is a 1.8V (1.8V-5.5V) 64K-bit (8192 x 8)
Electrically Erasable PROM, IS24C64-3 is a 2.5V (2.5V-
5.5V) 64K-bit (8192 x 8) Electrically Erasable PROM,
IS24C32-2 is a 1.8V (1.8V-5.5V) 32K-bit (4096 x 8)
Electrically Erasable PROM and the IS24C32-3 is a 2.5V
(2.5V-5.5V) 32K-bit (4096 x 8) Electrically Erasable
PROM.
The IS24CXX (IS24C64-2, IS24C64-3, IS24C32-2 and
IS24C32-3) family is a low-cost and low voltage 2-wire
Serial EEPROM. It is fabricated using ISSI’s advanced
CMOS EEPROM technology and provides a low power
and low voltage operation. The IS24CXX family features
a write protection feature, and is available in 8-pin DIP and
8-pin SOIC packages.
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
04/04/01
1

1 Page





IS24C64-2 pdf, ピン配列
IS24C32-2/3
IS24C64-2/3
ISSI ®
DEVICE OPERATION
The IS24CXX family features a serial communication and
supports a bi-directional 2-wire bus transmission protocol.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and a Serial
ClockLine(SCL). Theprotocoldefinesanydevicethatsendsdata
onto the SDA bus as a transmitter, and the receiving devices as a
receiver. ThebusiscontrolledbyMASTERdevicewhichgenerates
the SCL, controls the bus access and generates the STOP and
STARTconditions. TheIS24CXXistheSLAVEdeviceonthebus.
The Bus Protocol:
Data transfer may be initiated only when the bus is not busy
During a data transfer, the data line must remain stable
whenever the clock line is high. Any changes in the
data line while the clock line is high will be interpreted
as a START or STOP condition.
The state of the data line represents valid data when after
a START condition, the data line is stable for the duration
of the HIGH period of the clock signal. The data on the
SDA line may be changed during the LOW period of the
clock signal. There is one clock pulse per bit of data. Each
data transfer is initiated with a START condition and
terminated with a STOP condition.
START Condition
The START condition precedes all commands to the device
and is defined as a HIGH to LOW transition of SDA when
SCL is HIGH. The IS24CXX monitors the SDA and SCL
lines and will not respond until the START condition is met.
STOP Condition
The STOP condition is defined as a LOW to HIGH
transition of SDA when SCL is HIGH. All operations must
end with a STOP condition.
ACKnowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line.
DEVICE ADDRESSING
The MASTER begins a transmission by sending a START
condition. TheMASTERthensendstheaddressoftheparticular
slavedevicesitisrequesting. TheSLAVE(Fig.5)addressis8bits.
The four most significant bits of the address are fixed as
1010 for the IS24CXX.
The 32K/64K uses the three device address bits A2, A1,
A0 to allow as many as eight devices on the same bus.
These bits must compare to their corresponding hardwired
input pins. The A2, A1, and A0 pins use an internal
proprietary circuit that biases them to a logic low condition
if the pins are allowed to float.
The last bit of the slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the MASTER sends a START condition and the
SLAVE address byte, the IS24CXX monitors the bus and
responds with an Acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
IS24CXX pulls down the SDA line during the ninth clock
cycle, signaling that it received the eight bits of data. The
IS24CXX then performs a Read or Write operation
depending on the state of the R/W bit.
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the START
condition and the slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an acknowledge, the Master sends two byte addresses that
are to be written into the address pointer of the
IS24CXX. After receiving another acknowledge from the
Slave, the Master device transmits the data byte to be written
intotheaddressmemorylocation. TheIS24CXXacknowledges
once more and the Master generates the STOP condition,
at which time the device begins its internal programming
cycle. While this internal cycle is in progress, the device
will not respond to any request from the Master device.
Page Write
The IS24CXX is capable of 32-byte page-WRITE operation.
A page-WRITE is initiated in the same manner as a byte
write, but instead of terminating the internal write cycle after
the first data word is transferred, the master device can
transmit up to 31 more bytes. After the receipt of each data
word, the IS24CXX responds immediately with an
ACKnowledge on SDA line, and the five lower order data
word address bits are internally incremented by one, while
the five higher order bits of the data word address remain
constant. If the master device should transmit more than
32 words, prior to issuing the STOP condition, the address
counter will roll over,and the previously written data will
be overwritten. Once all 32 bytes are received and the
STOP condition has been sent by the Master, the internal
programming cycle begins. At this point, all received data
is written to the IS24CXX in a single write cycle. All inputs
are disabled until completion of the internal WRITE cycle.
Integrated Silicon Solution, Inc. 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
04/04/01
3


3Pages


IS24C64-2 電子部品, 半導体
IS24C32-2/3
IS24C64-2/3
Figure 4. Data Validity Protocol
SCL
SDA
Data Change
Data Stable
Data Stable
Figure 5. Slave Address
BIT 7 6 5 4 3 2 1 0
1 0 1 0 A2 A1 A0 R/W
ISSI ®
Figure 6. Byte Write
S
T
A
R
T
SDA
Bus
Activity
M
S
B
Device
Address
W
R
I
T
E
Word Address
Word Address
A
C***#
K
A
C
K
A
C
K
LM
S
B
S
B
R/W
* = Don't care bits
# = Don't care bit for 24C32
Data
S
T
O
P
A
C
K
Figure 7. Page Write
S
T
A
R
T
SDA
Bus
Activity
Device
Address
W
R
I
T
E Word Address (n) Word Address (n)
A AA
C***#
K
C
K
C
K
ML
SS
BB
R/W
* = Don't care bits
# = Don't care bit for 24C32
Data (n)
A
C
K
Data (n+1)
A
C
K
Data (n+31)
S
T
O
P
A
C
K
6 Integrated Silicon Solution, Inc. 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
04/04/01

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
IS24C64-2

65/536-bit/32/768-bit 2-WIRE SERIAL CMOS EEPROM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS24C64-2

65/536-bit/32/768-bit 2-WIRE SERIAL CMOS EEPROM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS24C64-3

65/536-bit/32/768-bit 2-WIRE SERIAL CMOS EEPROM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc
IS24C64-3

65/536-bit/32/768-bit 2-WIRE SERIAL CMOS EEPROM

Integrated Silicon Solution  Inc
Integrated Silicon Solution Inc


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