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intel387 の電気的特性と機能

intel387のメーカーはIntel Corporationです、この部品の機能は「Intel387TM SX MATH COPROCESSOR」です。


製品の詳細 ( Datasheet PDF )

部品番号 intel387
部品説明 Intel387TM SX MATH COPROCESSOR
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 




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intel387 Datasheet, intel387 PDF,ピン配置, 機能
Intel387TM SX
MATH COPROCESSOR
Y New Automatic Power Management
Low Power Consumption
Typically 100 mA in Dynamic Mode
and 4 mA in Idle Mode
Y Socket Compatible with Intel387 Family
of Math CoProcessors
Hardware and Software Compatible
Supported by Over 2100 Commercial
Software Packages
10% to 15% Performance Increase
on Whetstone and Livermore
Benchmarks
Y Compatible with the Intel386TM SX
Microprocessor
Extends CPU Instruction Set to
Include Trigonometric Logarithmic
and Exponential
Y High Performance 80-Bit Internal
Architecture
Y Implements ANSI IEEE Standard
754-1985 for Binary Floating-Point
Arithmetic
Y Available in a 68-Pin PLCC Package
See Intel Packaging Specification Order 231369
The Intel387TM SX Math CoProcessor is an extension to the Intel386TM SX microprocessor architecture The
combination of the Intel387TM SX with the Intel386TM SX microprocessor dramatically increases the process-
ing speed of computer application software that utilizes high performance floating-point operations An internal
Power Management Unit enables the Intel387TM SX to perform these floating-point operations while maintain-
ing very low power consumption for portable and desktop applications The internal Power Management Unit
effectively reduces power consumption by 95% when the device is idle
The Intel387TM SX Math CoProcessor is available in a 68-pin PLCC package and is manufactured on Intel’s
advanced 1 0 micron CHMOS IV technology
240225 – 22
Intel386 and Intel387 are trademarks of Intel Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
January 1994
Order Number 240225-009
COPYRIGHT INTEL CORPORATION 1995
1

1 Page





intel387 pdf, ピン配列
CONTENTS
PAGE
4 4 Bus Cycles
26
4 4 1 Intel387 SX Math
CoProcessor Addressing
27
4 4 2 CPU Math CoProcessor
Synchronization
27
4 4 3 Synchronous Asynchronous
Modes
27
4 4 4 Automatic Bus Cycle
Termination
27
5 0 BUS OPERATION
5 1 Non-pipelined Bus Cycles
5 1 1 Write Cycle
5 1 2 Read Cycle
5 2 Pipelined Bus Cycles
5 3 Mixed Bus Cycles
5 4 BUSY and PEREQ Timing
Relationship
27
28
28
29
29
30
32
6 0 PACKAGE SPECIFICATIONS
6 1 Mechanical Specifications
6 2 Thermal Specifications
33
33
33
CONTENTS
PAGE
7 0 ELECTRICAL
CHARACTERISTICS
7 1 Absolute Maximum Ratings
7 2 D C Characteristics
7 3 A C Characteristics
33
33
34
35
8 0 Intel387 SX MATH COPROCESSOR
INSTRUCTION SET
41
APPENDIX A Intel387 SX MATH
COPROCESSOR COMPATIBILITY
A 1 8087 80287 Compatibility
A 1 1 General Differences
A 1 2 Exceptions
A-1
A-1
A-1
A-2
APPENDIX B COMPATIBILITY
BETWEEN THE 80287 AND 8087
MATH COPROCESSOR
B-1
3
3


3Pages


intel387 電子部品, 半導体
Intel387TM SX MATH COPROCESSOR
1 1 Pin Description Table
The following table lists a brief description of each
pin on the Intel387 SX Math CoProcessor For a
more complete description refer to Section 4 1 Sig-
nal Description The following definitions are used in
these descriptions
The signal is active LOW
I Input Signal
O Output Signal
I O Input and Output Signal
Symbol
ADS
BUSY
CKM
CMD0
CPUCLK2
D15 – D0
ERROR
NC
NPS1
NPS2
NUMCLK2
PEREQ
READY
READYO
RESETIN
STEN
WR
VCC
VSS
Type
I
O
I
I
I
IO
O
I
I
I
O
I
O
I
I
I
I
I
Name and Function
ADDRESS STROBE indicates that the address and bus cycle definition is valid
BUSY indicates that the Math CoProcessor is currently executing an instruction
CLOCKING MODE is used to select synchronous or asynchronous clock modes
COMMAND determines whether an opcode or operand are being sent to the Math
CoProcessor During a read cycle it indicates which register group is being read
CPU CLOCK input provides the timing for the bus interface unit and the execution
unit in synchronous mode
DATA BUS is used to transfer instructions and data between the Math
CoProcessor and CPU
ERROR signals that an unmasked exception has occurred
NO CONNECT should always remain unconnected Connection of a N C pin may
cause the Math CoProcessor to malfunction or be incompatible with future
steppings
NPX SELECT 1 is used to select the Math CoProcessor
NPX SELECT 2 is used to select the Math CoProcessor
NUMERICS CLOCK is used in asynchronous mode to drive the Floating Point
Execution Unit
PROCESSOR EXTENSION REQUEST signals the CPU that the Math
CoProcessor is ready for data transfer to from its FIFO
READY indicates that the bus cycle is being terminated
READY OUT signals the CPU that the Math CoProcessor is terminating the bus
cycle
SYSTEM RESET terminates any operation in progress and forces the Math
CoProcessor to enter a dormant state
STATUS ENABLE serves as a master chip select for the Math CoProcessor
When inactive this pin forces all outputs and bi-directional pins into a floating
state
WRITE READ indicates whether the CPU bus cycle in progress is a read or a write
cycle
SYSTEM POWER provides the a5V nominal D C supply input
SYSTEM GROUND provides the 0V connection from which all inputs and outputs
are measured
6
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
INTEL386

Intel386 EX Embedded Microprocessor

Intel Corporation
Intel Corporation
INTEL386DX

32-bit Chmos Microprocessor

Intel Corporation
Intel Corporation
intel387

Intel387TM SX MATH COPROCESSOR

Intel Corporation
Intel Corporation
INTEL387TMDX

Intel387TM DX MATH COPROCESSOR

Intel Corporation
Intel Corporation


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