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PDF INT100S Data sheet ( Hoja de datos )
| Número de pieza | INT100S | |
| Descripción | Low-Side and High-side Drive with Simultaneous Conduction Lockout | |
| Fabricantes | Power Integrations Inc. | |
| Logotipo |  |
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INT100
®
Half-Bridge Driver IC
Low-Side and High-side Drive
with Simultaneous Conduction Lockout
Product Highlights
5 V CMOS Compatible Control Inputs
• Combines logic inputs for low and high-side drives
• Schmidt-triggered inputs for noise immunity
HV
Built-in High-voltage Level Shifters
• Can withstand up to 800 V for direct interface to the HV-
referenced high-side switch
• Pulsed internal high-voltage level shifters reduce power
consumption
Gate Drive Outputs for External MOSFETs
• Provides 300 mA sink/150 mA source current
• Can drive MOSFET gates at up to 15 V
• External MOSFET allows flexibility in design for various
motor sizes
VDD
HS IN
LS IN
COM
VDDH
HS OUT
HS RTN
LS OUT
LS
RTN
INT100
Built-in Protection Features
• Simultaneous conduction lockout protection
• Undervoltage lockout
Description
The INT100 half-bridge driver IC provides gate drive for
external low-side and high-side MOSFET switches. The INT100
provides a simple, cost-effective interface between low-voltage
control logic and high-voltage loads. The INT100 is designed
to be used with rectified 110 V or 220 V supplies. Both high-
side and low-side switches can be controlled independently
from ground-referenced 5 V logic inputs.
Built-in protection logic prevents both switches from turning
on at the same time and shorting the high voltage supply. Pulsed
internal level shifting saves power and provides enhanced noise
immunity. The circuit is powered from a nominal 15 V supply
to provide adequate gate drive for external N-channel MOSFETs.
A floating high-side supply is derived from the low-voltage rail
by using a simple bootstrap technique.
Figure 1. Typical Application
VDD
HS IN
LS IN
COM
COM
N/C
LS RTN
LS OUT
1
2
3
4
5
6
7
8
Figure 2. Pin Configuration.
PI-1807-031296
16 N/C
15 VDDH
14 HS RTN
13 HS RTN
12 HS RTN
11 HS OUT
10 N/C
9 N/C
PI-1067-101493
Applications for the INT100 include motor drives, electronic
ballasts, and uninterruptible power supplies. Multiple devices
can also be used to implement full-bridge and multi-phase
configurations.
The INT100 is available in a 16-pin plastic SOIC package.
ORDERING INFORMATION
PART
NUMBER
PACKAGE
OUTLINE
ISOLATION
VOLTAGE
INT100S
S16A
800 V
June 1996
1 page  
General Circuit Operation
One phase of a three-phase motor drive
circuit is shown in Figure 4 to illustrate
an application of the INT100. The LS
IN signal directly controls MOSFET
Q1. The HS IN signal controls MOSFET
Q2 via the high voltage level shift
transistors communicating with the high-
side driver. The INT100 will ignore
input signals that would command both
Q1 and Q2 to conduct simultaneously,
protecting against shorting the HV+ bus
to HV-.
Local bypassing for the low-side driver
is provided by C1. Bootstrap bias for the
high-side driver is provided by D1 and
C2. Slew rate and effects of parasitic
oscillations in the load waveforms are
controlled by resistors R1 and R2.
The inputs are designed to be compatible
with 5 V CMOS logic levels and should
not be connected to VDD. Normal CMOS
power supply sequencing should be
observed. The order of signal application
should be VDD, logic signals, and then
HV+. VDD should be supplied from a
low impedance voltage source.
The output returns (HS RTN and LS
RTN) are isolated from one another by
the internal high-voltage MOSFET level
shifters. The level shift circuitry is
designed to operate properly even when
the HS RTN swings as much as 5 V
below the LS RTN pin with VDDH biased
at 15 V. The INT100 will also safely
tolerate more negative voltages (as low
as -VDDH below LS RTN).
Maximum frequency of operation is
limited by power dissipation due to high-
voltage switching, gate charge, and bias
power. Figure 5 indicates the maximum
switching frequency as a function of
input voltage and gate charge. For higher
ambient temperatures, the switching
frequency should be derated linearly.
INT100
The bootstrap capacitor must be large
enough to provide bias current over the
entire on-time of the high-side driver
without significant voltage sag or decay.
The high-side MOSFET gate charge
must also be supplied at the desired
switching frequency. Figure 6 shows
the maximum high-side on-time versus
gate charge of the external MOSFET.
Applications with extremely long high-
side on times require special techniques
discussed in AN-10.
The high-side driver is latched on and
off by the edges of the appropriate low-
side logic signal. The high-side driver
will latch off and stay off if the bootstrap
capacitor discharges below the
undervoltage lockout threshold.
Undervoltage lockout-induced turn off
can occur during conditions such as
power ramp up, motor start, or low speed
operation.
CBOOTSTRAP vs. ON TIME
1000
100
10
QG = 100 nC
1
QG = 20 nC
0.1
0.01
0.01
0.1 1 10
High Side On Time (ms)
100
Figure 6. High-side On Time versus Bootstrap Capacitor.
5C
6/96
5 Page 
Notes
INT100
11C
6/96
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet INT100S.PDF ] | |
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