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PDF INA-02186-TR1 Data sheet ( Hoja de datos )
| Número de pieza | INA-02186-TR1 | |
| Descripción | Low Noise/ Cascadable Silicon Bipolar MMIC Amplifier | |
| Fabricantes | Agilent(Hewlett-Packard) | |
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Low Noise, Cascadable
Silicon Bipolar MMIC Amplifier
Technical Data
INA-02184
INA-02186
Features
• Cascadable 50 Ω Gain Block
• Low Noise Figure:
2.0 dB Typical at 0.5 GHz
• High Gain:
31 dB Typical at 0.5 GHz
26 dB Typical at 1.5 GHz
• 3 dB Bandwidth:
DC to 0.8 GHz
• Unconditionally Stable
(k>1)
• Low Cost Plastic Package
Description
The INA-02184 and INA-02186 are
low-noise silicon bipolar Mono-
lithic Microwave Integrated
Circuit (MMIC) feedback amplifi-
ers housed in low cost plastic
packages. They are designed for
narrow or wide bandwidth
commercial applications that
require high gain and low noise IF
or RF amplification.
Package 84
The INA series of MMICs is
fabricated using HP’s 10 GHz fT,
25 GHz fMAX, ISOSAT™-I silicon
bipolar process which uses nitride
self-alignment, submicrometer
lithography, trench isolation, ion
implantation, gold metallization
and polyimide intermetal dielec-
tric and scratch protection to
achieve excellent performance,
uniformity and reliability.
Package 86
Typical Biasing Configuration
VCC
RFC (Optional)
RF IN
Cblock
4
3
1
2
Rbias
Cblock
Vd = 5.5 V
RF OUT
5965-9675E
6-96
1 page  
Emitter Inductance and
Performance
As a direct result of their circuit
topology, the performance of INA
MMICs is extremely sensitive to
groundpath (“emitter”) induc-
tance. The two stage design
creates the possibility of a feed-
back loop being formed through
the ground returns of the stages. If
the path to ground provided by
the external circuit is “long” (high
in impedance) compared to the
path back through the ground
return of the other stage, then
instability can occur (see Fig. 1).
This phenomena can show up as a
“peaking” in the gain versus
frequency response (perhaps
creating a negative gain slope
amplifier), an increase in input
VSWR, or even as return gain (a
reflection coefficient greater than
unity) at the input of the MMIC.
The “bottomline” is that excellent
grounding is critical when
using INA MMICs. The use of
plated through holes or equivalent
minimal path ground returns at
the device is essential. An
appropriate layout is shown in
Figure 2. A corollary is that
designs should be done on the
thinnest practical substrate. The
parasitic inductance of a pair of
via holes passing through 0.032"
thick P.C. board is approximately
0.1 nH, while that of a pair of via
holes passing through 0.062" thick
board is close to 0.5 nH. HP does
not recommend using INA family
MMICs on boards thicker than
32␣ mils.
These stability effects are entirely
predictable. A circuit simulation
using the data sheet S-parameters
and including a description of the
ground return path (via model or
equivalent “emitter” inductance)
will give an accurate picture of the
performance that can be ex-
pected. Device characterizations
are made with the ground leads of
the MMIC directly contacting a
solid copper block (system
ground) at a distance of 2 to 4 mils
from the body of the package.
Thus the information in the data
sheet is a true description of the
performance capability of the
MMIC, and contains minimal
contributions from fixturing.
Figure 1. INA Potential
Ground Loop.
Figure 2. INA Circuit Board 2x
Actual Size.
6-100
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet INA-02186-TR1.PDF ] | |
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