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PDF IVC102 Data sheet ( Hoja de datos )
| Número de pieza | IVC102 | |
| Descripción | PRECISION SWITCHED INTEGRATOR TRANSIMPEDANCE AMPLIFIER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IVC102 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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® IVC102
PRECISION SWITCHED INTEGRATOR
TRANSIMPEDANCE AMPLIFIER
APPLICATIONS
q PRECISION LOW CURRENT MEASUREMENT
q PHOTODIODE MEASUREMENTS
q IONIZATION CHAMBER MEASUREMENTS
q CURRENT/CHARGE-OUTPUT SENSORS
q LEAKAGE CURRENT MEASUREMENT
FEATURES
q ON-CHIP INTEGRATING CAPACITORS
q GAIN PROGRAMMED BY TIMING
q LOW INPUT BIAS CURRENT: 750fA max
q LOW NOISE
q LOW SWITCH CHARGE INJECTION
q FAST PULSE INTEGRATION
q LOW NONLINEARITY: 0.005% typ
q 14-PIN DIP, SO-14 SURFACE MOUNT
DESCRIPTION
The IVC102 is a precision integrating amplifier with
FET op amp, integrating capacitors, and low leakage
FET switches. It integrates low-level input current for
a user-determined period, storing the resulting voltage
on the integrating capacitor. The output voltage can be
held for accurate measurement. The IVC102 provides
a precision, lower noise alternative to conventional
transimpedance op amp circuits that require a very
high value feedback resistor.
The IVC102 is ideal for amplifying low-level sensor
currents from photodiodes and ionization chambers.
The input signal current can be positive or negative.
TTL/CMOS-compatible timing inputs control the inte-
gration period, hold and reset functions to set the
effective transimpedance gain and to reset (discharge)
the integrator capacitor.
Package options include 14-Pin plastic DIP and SO-14
surface-mount packages. Both are specified for the
–40°C to 85°C industrial temperature range.
Ionization
Chamber
6 C3 60pF
VB
5 C2 30pF
4 C1 10pF
3
IIN 2
1
S1
S2
Photodiode
Analog
Ground
11 12
S1 S2
Logic Low closes switches
V+
14
10
VO
9
13 V–
Digital
Ground
∫V
O=
–1
CINT
IIN(t) dt
Positive or Negative
Signal Integration
0V
Hold Integrate Hold
S1
S2
Reset
InternationalAirportIndustrialPark • MailingAddress:POBox11400 • Tucson,AZ85734 • StreetAddress:6730S.TucsonBlvd. • Tucson,AZ 85706
Tel:(520)746-1111 • Twx:910-952-1111 • Cable:BBRCORP • Telex:066-6491 • FAX:(520)889-1510 • ImmediateProductInfo:(800)548-6132
© 1996 Burr-Brown Corporation
PDS-11329A
IVC102Printed in U.S.A. June, 1996
®
1 page  
APPLICATION INFORMATION
Figure 1 shows the basic circuit connections to operate the
IVC102. Bypass capacitors are shown connected to the
power supply pins. Noisy power supplies should be avoided
or decoupled and carefully bypassed.
The Analog Ground terminal, pin 1, is shown internally
connected to the non-inverting input of the op amp. This
terminal connects to other internal circuitry and should be
connected to ground. Approximately 200µA flows out of
this terminal.
Digital Ground, pin 13, should be at the same voltage
potential as analog ground (within 100mV). Analog and
Digital grounds should be connected at some point in the
system, usually at the power supply connections to the
circuit board. A separate Digital Ground is provided so that
noisy logic signals can be referenced to separate circuit
board traces.
Integrator capacitors C1, C2 and C3 are shown connected in
parallel for a total CINT = 100pF. The IVC102 can be used
for a wide variety of integrating current measurements. The
input signal connections and control timing and CINT value
will depend on the sensor or signal type and other applica-
tion details.
BASIC RESET-AND-INTEGRATE MEASUREMENT
Figure 1 shows the circuit and timing for a simple reset-and-
integrate measurement. The input current is connected di-
rectly to the inverting input of the IVC102, pin 3. Input
current is shown flowing out of pin 3, which produces a
positive-going ramp at VO. Current flowing into pin 3 would
produce a negative-going ramp.
A measurement cycle starts by resetting the integrator output
voltage to 0V by closing S2 for 10µs. Integration of the input
current begins when S2 opens and the input current begins to
charge CINT. VO is measured with a sampling a/d converter
at the end of an integration period, just prior to the next reset
period. The ideal result is proportional to the average input
current (or total accumulated charge).
Switch S2 is again closed to reset the integrator output to 0V
before the next integration period.
This simple measurement arrangement is suited to many
applications. There are, however, limitations to this basic
approach. Input current continues to flow through S2 during
the reset period. This leaves a small voltage on CINT equal
to the input current times RS2, the on-resistance of S2,
approximately 1.5kΩ.
Figure 1a
6 C3 60pF
5 C2 30pF
V+
+15V
0.1µF
14
Photodiode
Charge Injection
of S2
4
IIN
3
2
1
Analog
Ground
C1 10pF
S2
S1
11
Logic
High
(+5V)
10 VO
9
12 13
S2
See timing
signal below
Digital
Ground
0.1µF
–15V
V–
0V
Op Amp VOS
+
IIN • RS2
Figure 1b
T2
Sampling
A/D
Converter
Digital
Data
VO
0V
T1
Integrate
S2
10µs
Reset
(S2 Open)
FIGURE 1. Reset-and Integrate Connections and Timing.
5
10µs
Reset
IVC102
®
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet IVC102.PDF ] | |
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