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PDF ispPAC10-01PI Data sheet ( Hoja de datos )
| Número de pieza | ispPAC10-01PI | |
| Descripción | In-System Programmable Analog Circuit | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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ispPAC ®10
In-System Programmable Analog Circuit
Features
• IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG CIRCUIT
— Four Instrument Amplifier Gain/Attenuation Stages
— Signal Summation (Up to 4 Inputs)
— Precision Active Filtering (10kHz to 100kHz)
— No External Components Needed for Configuration
— Non-Volatile E2CMOS® Cells (10,000 Cycles)
— IEEE 1149.1 JTAG Serial Port Programming
• FOUR LINEAR ELEMENT BUILDING BLOCKS
— Programmable Gain Range (0dB to 80dB)
— Bandwidth of 550kHz (G=1), 330kHz (G=10)
— Low Distortion (THD < -74dB max @ 10kHz)
— Auto-Calibrated Input Offset Voltage
• TRUE DIFFERENTIAL I/O (±3V RANGE)
— High CMR (69dB) Instrument Amplifier Inputs
— 2.5V Common Mode Reference on Chip
— Four Rail-to-Rail Voltage Outputs
• 28-PIN PLASTIC DIP OR SOIC PACKAGE
— Single Supply 5V Operation
• APPLICATIONS INCLUDE INTEGRATED:
— Single +5V Supply Signal Conditioning
— Active Filters, Gain Stages, Summing Blocks
— Analog Front Ends, 12-Bit Data Acq. Systems
— Sensor Signal Conditioning
Description
Functional Block Diagram
OUT2+ 1
OUT2– 2
IN2+ 3
IN2– 4
TDI 5
TRST 6
VS 7
TDO 8
TCK 9
TMS 10
IN4– 11
IN4+ 12
OUT4– 13
OUT4+ 14
OA OA
IA IA
IA IA
Configuration Memory
Analog Routing Pool
Reference & Auto-Calibration
IA IA
IA IA
OA OA
28 OUT1+
27 OUT1–
26 IN1+
25 IN1–
24 TEST
23 TEST
22 VREFOUT
21 GND
20 CAL
19 CMVIN
18 IN3–
17 IN3+
16 OUT3–
15 OUT3+
The ispPAC10 is a member of the Lattice family of In-
System Programmable analog circuits, digitally configured
via nonvolatile E2CMOS technology.
Typical Application Diagram
Analog function modules, called PACblocks™, replace
traditional analog components such as op amps and
active filters, eliminating the need for most external
resistors and capacitors. With no requirement for exter-
nal configuration components, ispPAC10 expedites the
design process, simplifying prototype circuit implemen-
tation and change, while providing high performance and
integrated functionality.
Vin
5V
5V
12-Bit
Differential
Input ADC
Ain+
Ain-
Designers configure the ispPAC10 and verify its perfor-
mance using PAC-Designer®, an easy-to-use, Microsoft
Windows® compatible development tool. Device pro-
gramming is supported using PC parallel port I/O
operations. A library of configurations is included with basic
solutions and examples of advanced circuit techniques.
Ref+
The ispPAC10 is configured through its IEEE Standard
1149.1 (JTAG) compliant serial port. The flexible In-
System Programming capability enables programming,
verification and reconfiguration if desired, directly on the
printed circuit board.
ispPAC10
Ref-
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
pac10_04
1
1 page  
Specifications ispPAC10
Pin Descriptions
Pin Symbol
Name
Description
1 OUT2+ Output 2(+)
2 OUT2-
3 IN2+
4 IN2-
5 TDI
Output 2(-)
Input 2(+)
Input 2(-)
Test Data In
Differential output pin, VOUT+. (Plus complement of VOUT with respect to VREFOUT,
where differential VOUT = VOUT+ - VOUT-).
Differential output pin, VOUT-. (Minus component, where differential VOUT = VOUT+ - VOUT-).
Differential input pin, VIN+. (Plus VIN, where differential VIN = VIN+ - VIN-).
Differential input pin, VIN-. (Minus component of differential VIN, where VIN = VIN+ - VIN-).
Serial interface logic input pin. Input data valid on rising edge of TCK.
6 TRST
Test Reset
Serial interface logic reset pin (input). Asynchronously resets logic controller. Active low.
Reset is equivalent of power-on default.
7 VS
Supply Voltage
Analog supply voltage pin (5V nominal).
Should be bypassed to GND with 1µF and .01µF capacitors.
8 TDO
Test Data Out
Serial interface logic output pin. Input data valid on falling edge of TCK.
9 TCK
Test Clock
Serial interface logic clock pin (input). Best analog performance when TCK is idle.
10 TMS
Test Mode Select
Serial interface logic mode select pin (input).
11 IN4-
12 IN4+
13 OUT4-
14 OUT4+
15 OUT3+
16 OUT3-
17 IN3+
18 IN3-
19 CMVIN
Input 4(-)
Input 4(+)
Output 4(-)
Output 4(+)
Output 3(+)
Output 3(-)
Input 3(+)
Input 3(-)
Input for VCM Reference
Differential input pin, VIN-
Differential input pin, VIN+
Differential output pin, VOUT-
Differential output pin, VOUT+
Differential output pin, VOUT+
Differential output pin, VOUT-
Differential input pin, VIN+
Differential input pin, VIN-
Input pin for optional (external) analog Common-Mode Voltage (VCM). Replaces VREFOUT
(+2.5V) for any so programmed PACblock as its common-mode output voltage value.
20 CAL
Auto-Calibrate
Digital input pin. Commands an auto-calibration sequence on a rising edge.
21 GND
Ground
Ground pin. Should normally be connected to analog ground plane.
22 VREFOUT Common-Mode Reference Common-mode voltage reference output pin (+2.5V nominal). Must be bypassed to GND
with a 0.1µF capacitor.
23 TEST
Test Pin
Manufacturing test pin. Connect to GND for proper circuit operation.
24 TEST
Test Pin
Manufacturing test pin. Connect to GND for proper circuit operation.
25 IN1-
26 IN1+
27 OUT1-
28 OUT1+
Input 1(-)
Input 1(+)
Output 1(-)
Output 1(+)
Differential input pin, VIN-
Differential input pin, VIN+
Differential output pin, VOUT-
Differential output pin, VOUT+
Connection Notes
Pin Configuration
1. All inputs and outputs are labeled with plus (+) and
minus (-) signs. Polarity is labeled for reference and
can be selected externally by reversing pin connec-
tions or internally under user programmable control.
2. All analog output pins are “hard-wired” to internal
output devices and should be left open if not used.
Outputs of uncommitted PACblocks are forced to
VREFOUT (2.5V) and can be used as low impedance
reference output buffers. VOUT+ and VOUT- should not
be tied together as unnecessary power will be dissi-
pated.
3. When the signal input is single-ended, the other half of
the unused differential input must be connected to a
DC common-mode reference (usually VREFOUT, 2.5V).
OUT2+
OUT2–
IN2+
IN2–
TDI
TRST
VS (5V)
TDO
TCK
TMS
IN4–
IN4+
OUT4–
OUT4+
1
OUT1+
OUT1–
IN1+
IN1–
TEST (tie to GND)
TEST (tie to GND)
VREFout
GND (0V)
CAL
CMVin
IN3–
IN3+
OUT3–
OUT3+
28-Pin
Top View
5
5 Page 
Specifications ispPAC10
Theory of Operation (Continued)
- VIN gm1 + VOUT gm3 + (VOUT + – (V- ))sCF (3a) Figure 4. PAC-Designer FilSum PACblock
VIN gm1 - VOUT gm3 + (VOUT - – (V+))sCF (3b)
where V- and V+ are the voltages at the op amp inverting
and non-inverting inputs respectively. Because of feed-
back they are equal, so
-VIN gm1 + VOUT gm3 + (VOUT +sCF )
= VIN gm1 – VOUT gm3 + (VOUT - sCF )
(4)
PACblock
2
Two
Differential
Inputs
2
k1 Feedback Enable
CF 1pF to 62pF
IA1
Summation
IA2
k2
kN =–1, 2...10
RF
OA1
Differential
2 Output
2.5V Common-
Mode Voltage
Input
and the differential output voltage VOUT is the difference
VOUT+ - VOUT- ,
The FilSum PACblock implements two primary functions:
the lossy integrator (low pass filter) and the integrator,
both with gain.
VOUT =
gm1
VIN
gm3
+
sCF
2
(5a)
Since the PACblock has two separate inputs (IA1 and
IA2) summed at the output amplifier input:
VOUT
=
k1gm VIN1 + k 2gm VIN2
gm3
+
sCF
2
(5b)
Lossy Integrator. The lossy integrator’s schematic within
PAC-Designer is shown in Figure 5. Manipulating the
PACblock transfer function of Equation 5 to better show
the pole frequency yields:
VOUT =
k1VIN1 + k2VIN2
1+ sCF
2gm
(6)
Figure 5. PAC-Designer PACblock Lossy Integrator
The input amplifiers have a programmable gain of
k·2µA/V (gm1 and gm2) where k is an integer from -10 to
10. The feedback amplifier transconductance gm3 is fixed
at 2µA/V, but may be disabled (gm3 = 0) to open-circuit
the output amplifier’s resistive feedback. The program-
mable feedback capacitance lies in the range 1pF to
62pF.
VIN1
k1
IA1
VIN2
IA2
k2
CF
RF
OA1
2.5V
VOUT
The PACblock model from PAC-Designer is shown in
Figure 4. The output amplifier is configured as an invert-
ing mode op amp and illustrates the summing
configuration. The input instrument amplifiers are shown
to make it clear that unlike a typical inverting op amp, the
PACblock input impedance is extremely high. The input
amplifier (IA) transconductance (gain) is shown as the
value (k) above or below each amplifier. The gain of IA1
and IA2 are independently programmable. Because the
feedback transconductor IAF (designated here as RF)
can be disabled by the user, a user configurable switch
is shown in series.
The DC gain of each input is set by k1 or k2 respectively,
the gain constant for the input amplifiers. Below the pole
frequency, this circuit can be viewed as a gain block.
Because of the bandwidth trim capacitance, there is a
minimum value of CF causing the bandwidth to be ap-
proximately 550kHz when the DC gain is one. For larger
gains, the input amplifier bandwidth begins to dominate
the overall PACblock response, limiting the bandwidth to
about 330kHz when the gain is 10.
Examining this transfer function shows the pole fre-
quency is (1/2π)(2gm/C). Since gm = 2µA/V and 1pF ≤ CF
≤ 62pF, then 600kHz ≥ fP ≥ 10kHz. Due to the selection
options for feedback capacitance, there are at least 120
poles between 10kHz and 100kHz.
11
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| PDF Descargar | [ Datasheet ispPAC10-01PI.PDF ] | |
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