ispLSI5256VA-70LQ208 Datasheet PDF - Lattice Semiconductor
| Part Number | ispLSI5256VA-70LQ208 | |
| Description | In-System Programmable 3.3V SuperWIDE High Density PLD | |
| Manufacturers | Lattice Semiconductor | |
| Logo |  |
|
|
There is a preview and ispLSI5256VA-70LQ208 download ( pdf file ) link at the bottom of this page. Total 25 Pages | ||
Preview 1 page No Preview Available !
ispLSI® 5256VA
In-System Programmable
3.3V SuperWIDE™ High Density PLD
Features
• SuperWIDE HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 12000 PLD Gates / 256 Macrocells
— Up to 192 I/O Pins
— 256 Registers
— High-Speed Global Interconnect
— SuperWIDE 32 Generic Logic Block (GLB) Size for
Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package
Options
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns,
tsu3 (CLK2/3) = 3.5ns
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with Single-
Level Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports
up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Macrocell Registers Feature Multiple Control
Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell
Product Term Clocks
— Slew and Skew Programmable I/O (SASPI/O™)
Supports Programmable Bus Hold, Pull-up, Open
Drain and Slew and Skew Rate Options
— Six Global Output Enable Terms, Two Global OE
Pins and One Product Term OE per Macrocell
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Boundary
Scan
Interface
Global Routing Pool
(GRP)
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
ispLSI 5000V Description
The ispLSI 5000V Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are pro-
vided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and five extra control product terms. The GLB has 68
inputs from the Global Routing Pool which are available
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
5256va_04
1
|
| |
 
Specifications ispLSI 5256VA
Figure 3. ispLSI 5000V Generic Logic Block (GLB)
From Global Routing Pool
0 1 2 66 67
PT 0
PT 1
PT 2
PT 3
PT 4
PTSA
PT 9
PT 8
PT 7
PT 6
PT 5
Global PTOE Bus
Macrocell 0
From PTSA
PTSA bypass
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
6 Global PTOE 0 ... 5
Macrocell 1
From PTSA
PTSA bypass
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
Global PTOE 0 ... 5
6
To I/O Pad
To GRP
To I/O Pad
To GRP
PT 79
PT 78
PT 77
PT 76
PT 75
Macrocell 15
From PTSA
PTSA bypass
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
Global PTOE 0 ... 5
6
To I/O Pad
To GRP
PT 159
PT 158
PT 157
PT 156
PT 155
PT 160
PT 161
PT 162
PT 163
PT 164
Programmable
AND Array
Macrocell 31
From PTSA
PTSA bypass
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
6 Global PTOE 0 ... 5
To I/O Pad
To GRP
GLB_5K
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ispLSI5256VA-70LQ208 electronic component. |
| Information | Total 25 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ispLSI5256VA-70LQ208.PDF Datasheet ] | |
Share Link :
Electronic Components Distributor
|
An electronic components distributor is a company that sources, stocks, and sells electronic components to manufacturers, engineers, and hobbyists. |
| SparkFun Electronics | Allied Electronics | DigiKey Electronics | Arrow Electronics |
| Mouser Electronics | Adafruit | Newark | Chip One Stop |
Featured Datasheets
| Part Number | Description | MFRS |
| ispLSI5256VA-70LQ208 | The function is In-System Programmable 3.3V SuperWIDE High Density PLD. Lattice Semiconductor | |
Semiconductors commonly used in industry:
1N4148 |
BAW56 |
1N5400 |
NE555 | | ||
Quick jump to:
ispL
1N4
2N2
2SA
2SC
74H
BC
HCF
IRF
KA | ||