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ispLSI5256VA-125LB208 の電気的特性と機能

ispLSI5256VA-125LB208のメーカーはLattice Semiconductorです、この部品の機能は「In-System Programmable 3.3V SuperWIDE High Density PLD」です。


製品の詳細 ( Datasheet PDF )

部品番号 ispLSI5256VA-125LB208
部品説明 In-System Programmable 3.3V SuperWIDE High Density PLD
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ispLSI5256VA-125LB208 Datasheet, ispLSI5256VA-125LB208 PDF,ピン配置, 機能
ispLSI® 5256VA
In-System Programmable
3.3V SuperWIDE™ High Density PLD
Features
• SuperWIDE HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 12000 PLD Gates / 256 Macrocells
— Up to 192 I/O Pins
— 256 Registers
— High-Speed Global Interconnect
— SuperWIDE 32 Generic Logic Block (GLB) Size for
Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package
Options
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay
— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns,
tsu3 (CLK2/3) = 3.5ns
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with Single-
Level Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports
up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Macrocell Registers Feature Multiple Control
Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell
Product Term Clocks
— Slew and Skew Programmable I/O (SASPI/O™)
Supports Programmable Bus Hold, Pull-up, Open
Drain and Slew and Skew Rate Options
— Six Global Output Enable Terms, Two Global OE
Pins and One Product Term OE per Macrocell
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Boundary
Scan
Interface
Global Routing Pool
(GRP)
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
ispLSI 5000V Description
The ispLSI 5000V Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are pro-
vided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and five extra control product terms. The GLB has 68
inputs from the Global Routing Pool which are available
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
5256va_04
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ispLSI5256VA-125LB208 pdf, ピン配列
Specifications ispLSI 5256VA
ispLSI 5000V Description (Continued)
in both true and complement form for every product term.
The 160 product terms are grouped in 32 sets of five and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 35 product terms for
a single function. Alternatively, the PTSA can be by-
passed for functions of five product terms or less. The
five extra product terms are used for shared GLB con-
trols, set, reset, clock, clock enable and output enable.
The 32 registered macrocells in the GLB are driven by the
32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a pro-
grammable register/latch/toggle flip-flop and the
necessary clocks and control logic to allow combinatorial
or registered operation. The macrocells each have two
outputs, which can be fed back through the Global
Routing Pool. This dual output capability from the
macrocell allows efficient use of the hardware resources.
One output can be a registered function for example,
while the other output can be an unrelated combinatorial
function. A direct register input from the I/O pad facili-
tates efficient use of this feature to construct high-speed
input registers.
Macrocell registers can be clocked from one of several
global or product term clocks available on the device. A
global and product term clock enable is also provided,
eliminating the need to gate the clock to the macrocell
registers. Reset and preset for the macrocell register is
provided from both global and product term signals. The
macrocell register can be programmed to operate as a D-
type register, a D-type latch or a T-type flip flop.
The 32 outputs from the GLB can drive both the Global
Routing Pool and the device I/O cells. The Global
Routing Pool contains one line from each macrocell
output and one line from each I/O pin.
The input buffer threshold has programmable TTL/3.3V/
2.5V compatible levels. The output driver can source
4mA and sink 8mA in 3.3V mode. The output drivers
have a separate VCCIO reference input which is inde-
pendent of the main VCC supply for the device. This
feature allows the output drivers to drive either 3.3V or
2.5V output levels while the device logic and the output
current drive is always powered from 3.3V. The output
drivers also provide individually programmable edge
rates and open drain capability. A programmable pullup
resistor is provided to tie off unused inputs and a pro-
grammable bus-hold latch is available to hold tristate
outputs in their last valid state until the bus is driven again
by some device.
The ispLSI 5000V Family features 3.3V, non-volatile in-
system programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface. Boundary Scan test is also
supported through the same interface.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
ispLSI 5000V Family Members
The ispLSI 5000V Family ranges from 256 macrocells to
512 macrocells and operates from a 3.3V power supply.
All family members will be available with multiple pack-
age options. The ispLSI 5000V Family device matrix
showing the various bondout options is shown in the table
below.
The interconnect structure (GRP) is very similar to Lattice's
existing ispLSI 1000, 2000 and 3000 families, but with an
enhanced interconnect structure for optimal pin locking
and logic routing. This eliminates the need for registered
I/O cells or an Output Routing Pool.
Table 1. ispLSI 5000V Family
Device
ispLSI 5256VA
ispLSI 5384VA
ispLSI 5512VA
GLBs
8
12
16
Macrocells 208 fpBGA
256 144 I/O
384 144 I/O
512 —
Package Type
208 PQFP 272 BGA
144 I/O
192 I/O
144 I/O
192 I/O
144 I/O
192 I/O
388 BGA
288 I/O
288 I/O
3


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ispLSI5256VA-125LB208 電子部品, 半導体
Specifications ispLSI 5256VA
Figure 4. ispLSI 5000V Macrocell
PTOE
GOE0
GOE1
TOE
Global PTOE 0
Global PTOE 1
Global PTOE 2
Global PTOE 3
Global PTOE 4
Global PTOE 5
PTSA bypass
PTSA
Shared PT Clock 0
PT Clock Shared PT Clock 1
CLK0
CLK1
CLK2
CLK3
PT Reset
VCCIO VCC VCCIO
DQ
D/T
Clk En
R/L
Clk
RP
D
Delay
Slew Open
rate drain
2.5V/3.3V
Output
I/O Pad
To GRP
DQ
Q
Programmable
Speed/Power
Option
SET/RESET
PT Preset
Shared PT (P)reset 0
Shared PT (P)reset 1
D/T
Clk En
Clk
Register/
Latch
RP
6

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部品番号部品説明メーカ
ispLSI5256VA-125LB208

In-System Programmable 3.3V SuperWIDE High Density PLD

Lattice Semiconductor
Lattice Semiconductor


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