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PDF ispLSI3256A-70LQI Data sheet ( Hoja de datos )
| Número de pieza | ispLSI3256A-70LQI | |
| Descripción | In-System Programmable High Density PLD | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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ispLSI® 3256A
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 128 I/O Pins
— 11000 PLD Gates
— 384 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 90 MHz Maximum Operating Frequency
— tpd = 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 5V In-System Programmable (ISP™) using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Mini-
mize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool
H3 H2 H1 H0
Output Routing Pool
G3 G2 G1 G0
Boundary
Scan
A0 D Q F3
A1
DQ
OR
F2
A2
Array D Q
F1
DQ
A3
Twin
F0
D Q GLB
DQ
OR
B0
Array D Q
E3
B1 D Q E2
B2 E1
Global Routing Pool
B3 E0
C0 C1 C2 C3
Output Routing Pool
D0 D1 D2 D3
Output Routing Pool
Description
0139A
The ispLSI 3256A is a High-Density Programmable Logic
Device containing 384 Registers, 128 Universal I/O pins,
five Dedicated Clock Input Pins, eight Output Routing
Pools (ORP) and a Global Routing Pool (GRP) which
allows complete inter-connectivity between all of these
elements. The ispLSI 3256A features 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3256A offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 3256A device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.
There are a total of 32 Twin GLBs in the ispLSI 3256A
device. Each Twin GLB has 24 inputs, a programmable
AND array and two OR/Exclusive-OR Arrays, and eight
outputs which can be configured to be either combinato-
rial or registered. All Twin GLB inputs come from the
GRP.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
May 1999
3256a_09
1
1 page  
Specifications ispLSI 3256A
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.5V from
steady-state active level.
GND to 3.0V
≤ 3ns 10% to 90%
1.5V
1.5V
See Figure 2
Table 2-0003/3256A
Figure 2. Test Load
Device
Output
+ 5V
R1
R2
Test
Point
CL*
Output Load conditions (See Figure 2)
TEST CONDITION
A
Active High
B
Active Low
Active High to Z
C at VOH -0.5V
Active Low to Z
at VOL+0.5V
R1
470Ω
∞
470Ω
∞
R2
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
470Ω
390Ω 5pF
Table 2 - 0004A
*CL includes Test Fixture and Probe Capacitance.
0213A
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
MIN. TYP.3 MAX. UNITS
VOL
Output Low Voltage
IOL= 8 mA
– – 0.4 V
VOH
Output High Voltage
IOH = -4 mA
2.4 – – V
IIL
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
– – -10 µA
IIH
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
– – 10 µA
IIL-isp ispEN Input Low Leakage Current
0V ≤ VIN ≤ VIL
– – -150 µA
IIL-PU I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
– – -150 µA
IOS1
Output Short Circuit Current
VCC= 5V, VOUT = 0.5V
– – -200 mA
ICC2, 4 Operating Power Supply Current
VIL= 0.0V, VIH = 3.0V
Commercial
–
200
–
mA
fCLOCK = 1 MHz
Industrial
– 200 – mA
Table 2-0007/3256A
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using 16 16-bit counters.
3. Typical values are at VCC= 5V and TA= 25°C.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC .
5
5 Page 
Specifications ispLSI 3256A
Pin Description
NAME
I/O 0 - I/O 4
I/O 5 - I/O 9
I/O 10 - I/O 14
I/O 15 - I/O 19
I/O 20 - I/O 24
I/O 25 - I/O 29
I/O 30 - I/O 34
I/O 35 - I/O 39
I/O 40 - I/O 44
I/O 45 - I/O 49
I/O 50 - I/O 54
I/O 55 - I/O 59
I/O 60 - I/O 64
I/O 65 - I/O 69
I/O 70 - I/O 74
I/O 75 - I/O 79
I/O 80 - I/O 84
I/O 85 - I/O 89
I/O 90 - I/O 94
I/O 95 - I/O 99
I/O 100 - I/O 104
I/O 105 - I/O 109
I/O 110 - I/O 114
I/O 115 - I/O 119
I/O 120 - I/O 124
I/O 125 - I/O 127
GOE0 and GOE1
TOE
RESET
Y0, Y1 and Y2
Y3 and Y4
BSCAN/ispEN
TDI/SDI
TCK/SCLK
TMS/MODE
TRST
TDO/SDO
GND
VCC
PQFP/MQFP PIN NUMBERS
25, 26,
32, 33,
37, 38,
42, 43,
48, 49,
54, 55,
59, 60,
65, 66,
70, 72,
76, 77,
82, 83,
87, 88,
93, 94,
106, 108,
113, 114,
118, 119,
123, 124,
129, 130,
135, 136,
140, 141,
146, 147,
152, 153,
157, 158,
3, 4,
8, 9,
15, 16,
28, 29,
34, 35,
39, 40,
44, 46,
50, 52,
56, 57,
61, 62,
67, 68,
73, 74,
78, 79,
84, 85,
89, 90,
95, 96,
109, 110,
115, 116,
120, 121,
126, 127,
132, 133,
137, 138,
142, 144,
148, 149,
154, 155,
159, 160,
5, 6,
11, 13,
17
30,
36,
41,
47,
53,
58,
64,
69,
75,
80,
86,
92,
105,
112,
117,
122,
128,
134,
139,
145,
150,
156,
2,
7,
14,
100 and 99
98
20
18, 19, 103
102, 101
21
22
23
24
97
104
1, 10, 27, 45,
81, 107, 125, 143
12, 31, 51,
111, 131, 151
71,
63,
91,
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Global Output Enable input pins.
Test output enable pin - This pin tristates all I/O pins when a logic low is
driven
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock inputs. These clock inputs are connected to one of the
clock inputs of all the GLBs on the device.
Dedicated Clock inputs. These clock inputs are connected to one of the
clock inputs of all the I/O cells in the device.
Input – Dedicated in-system programming enable input pin. When this pin is high,
the BSCAN TAP controller pins TMS, TDI, TDO and TCK are enabled. When this
pin is brought low, the ISP state machine control pins MODE, SDI, SDO and
SLCK are enabled. High-to-low transition of this pin will put the device in the
programming mode and put all I/O pins in high-Z state.
Input – This pin performs two functions depending on the state of the
BSCAN/ispEN pin. It is the Test Data input to the TAP Controller when the ispEN
is logic high. TDI is used to load BSCAN test data or programming data. When
ispEN is logic low, it functions as an input pin to load programming data into the
ISP state machine.
Input – This pin performs two functions, depending on the state of the
BSCAN/ispEN pin. It is the Test Clock input pin when BSCAN/ispEN is logic high.
When BSCAN/ispEN is logic low, it functions as the clock for the ISP state
machine.
Input – This pin performs two functions, depending on the state of the
BSCAN/ispEN pin. It is the Test Mode Select input pin when BSCAN/ispEN is
logic high. When BSCAN/ispEN is logic low, it functions to control the operation of
the ISP state machine.
Input – Test Reset, active low to reset the Boundary Scan state machine.
Output – This pin performs two functions, depending on the state of the
BSCAN/ispEN pin. It is the Test Data Output pin when BSCAN/ispEN is logic high,
and either BSCAN test data or programming data is shifted out. When
BSCAN/ispEN is logic low, it is the Serial Data Output of the ISP state machine.
Ground (GND)
VCC
Table 2-0002/3256A.a
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ispLSI3256A-70LQI.PDF ] | |
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