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ispLSI2192VL-135LB144 の電気的特性と機能

ispLSI2192VL-135LB144のメーカーはLattice Semiconductorです、この部品の機能は「2.5V In-System Programmable SuperFAST High Density PLD」です。


製品の詳細 ( Datasheet PDF )

部品番号 ispLSI2192VL-135LB144
部品説明 2.5V In-System Programmable SuperFAST High Density PLD
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ispLSI2192VL-135LB144 Datasheet, ispLSI2192VL-135LB144 PDF,ピン配置, 機能
ispLSI® 2192VL
2.5V In-System Programmable
SuperFAST™ High Density PLD
Features
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 8000 PLD Gates
— 96 I/O Pins, Nine Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Pinout Compatible with ispLSI 2096V and 2096VE
• 2.5V LOW VOLTAGE ARCHITECTURE
— Interfaces with Standard 3.3V Devices (Inputs and
I/Os are 3.3V Tolerant)
— 175 mA Typical Active Current
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 150 MHz Maximum Operating Frequency
tpd = 6.0 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-
OR Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
A0
A1
A2
A3
Global Routing Pool (GRP)
A4
A5
A6
A7
DQ
DQ
Logic
Array D Q GLB
DQ
D7
D6
D5
D4
D3
D2
D1
D0
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool
0139/2192VL
Description
The ispLSI 2192VL is a High Density Programmable
Logic Device containing 192 Registers, nine Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2192VL fea-
tures in-system programmability through the Boundary
Scan Test Access Port (TAP) and is 100% IEEE 1149.1
Boundary Scan Testable. The ispLSI 2192VL offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2192VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 2192VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2192vl_02
1

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ispLSI2192VL-135LB144 pdf, ピン配列
Specifications ispLSI 2192VL
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................ -0.5 to +4.05V
Input Voltage Applied ............................. -0.5 to +4.05V
Off-State Output Voltage Applied .......... -0.5 to +4.05V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
VCC
VIL
VIH
Supply Voltage
Input Low Voltage
Input High Voltage
PARAMETER
Commercial
Industrial
TA = 0°C to + 70°C
TA = -40°C to + 85°C
Capacitance (TA=25°C, f=1.0 MHz)
MIN.
3.0
3.0
VSS 0.5
2.0
MAX. UNITS
3.6 V
3.6 V
0.8 V
5.25
V
Table 2-0005/2192VL
SYMBOL
C1
C2
C3
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
Clock and Global Output Enable Capacitance
TYPICAL
8
6
10
UNITS
pf
pf
pf
TEST CONDITIONS
VCC = 2.5V, VIN = 0.0V
VCC = 2.5V, VI/O = 0.0V
VCC = 2.5V, VY = 0.0V
Table 2-0006/2192VL
Erase Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
MINIMUM
10,000
MAXIMUM
UNITS
Cycles
Table 2-0008/2192VL
3


3Pages


ispLSI2192VL-135LB144 電子部品, 半導体
Specifications ispLSI 2192VL
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER #2
DESCRIPTION
Inputs
tio 20 Input Buffer Delay
tdin 21 Dedicated Input Delay
GRP
tgrp 22 GRP Delay
GLB
t4ptbpc
t4ptbpr
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
t1ptxor
t20ptxor
txoradj
tgbp
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay 3
28 GLB Register Bypass Delay
tgsu
tgh
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
tgco
31 GLB Register Clock to Output Delay
tgro
tptre
tptoe
tptck
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
ORP
torp
torpbp
36 ORP Delay
37 ORP Bypass Delay
Outputs
tob
tsl
toen
todis
tgoe
38 Output Buffer Delay
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
Clocks
tgy0
tgy1/2
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
Global Reset
tgr 45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
-150
-135
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
0.4
1.5
1.0
2.2
0.9
2.7
ns
ns
1.1 1.2 1.8 ns
2.5 3.2 5.2
3.0 3.2 4.7
4.0 4.2 6.2
4.0 4.2 6.2
4.0 4.2 6.2
0.0 0.5 1.0
1.2 1.7 1.7
2.8 3.3 4.8
0.3 0.3 0.3
0.6 1.1 4.3
4.9 6.6 8.9
5.0 5.8 7.4
1.2 4.2 2.1 4.5 2.8 4.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.4
0.4
1.5
0.5
1.5
0.5
ns
ns
1.6
2.0
3.5
3.5
2.5
1.6
2.0
4.0
4.0
3.0
1.6
2.0
4.9
4.9
4.1
ns
ns
ns
ns
ns
1.7 1.7 2.1 2.1 2.6 2.6
1.9 1.9 2.3 2.3 2.8 2.8
ns
ns
3.4
4.8
7.1 ns
Table 2-0036/2192VL
6

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部品番号部品説明メーカ
ispLSI2192VL-135LB144

2.5V In-System Programmable SuperFAST High Density PLD

Lattice Semiconductor
Lattice Semiconductor


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