PDF ispLSI2128VE-135LB208 Data sheet ( Hoja de datos )

Número de pieza	ispLSI2128VE-135LB208
Descripción	3.3V In-System Programmable SuperFAST High Density PLD
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispLSI® 2128VE 3.3V In-System Programmable SuperFAST™ High Density PLD Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 6000 PLD Gates — 128 and 64 I/O Pin Versions, Eight Dedicated Inputs — 128 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2128V Devices • 3.3V LOW VOLTAGE 2128 ARCHITECTURE — Interfaces with Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 250MHz Maximum Operating Frequency — tpd = 4.0ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired- OR Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram* Output Routing Pool (ORP) D7 D6 D5 D4 Output Routing Pool (ORP) D3 D2 D1 D0 A0 C7 A1 C6 A2 DQ C5 A3 C4 DQ Logic A4 Array DQ GLB C3 A5 C2 DQ A6 C1 A7 Global Routing Pool (GRP) C0 B0 B1 B2 B3 Output Routing Pool (ORP) B4 B5 B6 B7 Output Routing Pool (ORP) *128 I/O Version Shown Description 0139A/2128VE The ispLSI 2128VE is a High Density Programmable Logic Device available in 128 and 64 I/O-pin versions. The device contains 128 Registers, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedi- cated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2128VE features in-system programmability through the Bound- ary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2128VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable sys- tems. The basic unit of logic on the ispLSI 2128VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 2128VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com September 2000 2128ve_08 1 1 page Specifications ispLSI 2128VE External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 3 COND. # DESCRIPTION1 -250 -180 UNITS MIN. MAX. MIN. MAX. tpd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 4.0 — 5.0 ns tpd2 A 2 Data Propagation Delay — 6.0 — 7.5 ns fmax A 3 Clock Frequency with Internal Feedback 2 250 — 180 — MHz fmax (Ext.) fmax (Tog.) — 4 Clock Frequency with External Feedback (1 tsu2 + )tco1 — 5 Clock Frequency, Max. Toggle 158.7 — 125 275 — 200 — MHz — MHz tsu1 — 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 2.5 — 3.5 — ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass — 3.0 — 3.5 ns th1 — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 — 0.0 — ns tsu2 — 9 GLB Reg. Setup Time before Clock 3.3 — 4.5 — ns tco2 A 10 GLB Reg. Clock to Output Delay — 3.7 — 4.5 ns th2 — 11 GLB Reg. Hold Time after Clock 0.0 — 0.0 — ns tr1 A 12 Ext. Reset Pin to Output Delay, ORP Bypass — 6.0 — 7.0 ns trw1 — 13 Ext. Reset Pulse Duration 3.5 — 4.0 — ns tptoeen B 14 Input to Output Enable — 6.0 — 10.0 ns tptoedis C 15 Input to Output Disable — 6.0 — 10.0 ns tgoeen B 16 Global OE Output Enable — 4.0 — 5.0 ns tgoedis C 17 Global OE Output Disable — 4.0 — 5.0 ns twh — 18 External Synchronous Clock Pulse Duration, High 1.8 — 2.5 — ns twl — 19 External Synchronous Clock Pulse Duration, Low 1.8 — 2.5 — ns 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Table 2-0030A/2128VE v.1.0 5 5 Page Specifications ispLSI 2128VE Signal Descriptions Signal Name RESET GOE 0, GOE1 Y0, Y1, Y2 BSCAN TDI/IN 0 TCK/IN 3 TMS/IN 1 TDO/IN 2 IN 4 - IN 7 GND VCC NC1 I/O Description Active Low (0) Reset pin resets all the registers in the device. Global Output Enable input pins. Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in the device. Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input – This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. Input – This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Input – This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. Output/Input – This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Dedicated Input Pins to the device. Ground (GND) Vcc No Connect Input/Output Pins – These are the general purpose I/O pins used by the logic array. 1. NC pins are not to be connected to any active signals, VCC or GND. 11 11 Page

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