ispLSI2064VE-135LB100 Datasheet PDF - Lattice Semiconductor
| Part Number | ispLSI2064VE-135LB100 | |
| Description | 3.3V In-System Programmable High Density SuperFAST PLD | |
| Manufacturers | Lattice Semiconductor | |
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ispLSI® 2064VE
3.3V In-System Programmable
High Density SuperFAST™ PLD
Features
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible with
ispLSI 2064V Devices
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 280MHz* Maximum Operating Frequency
— tpd = 3.5ns* Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
*Advanced Information
Functional Block Diagram
Input Bus
Output Routing Pool (ORP)
B7 B6 B5 B4
A0
Global Routing Pool
(GRP)
B3
A1
A2 GLB
A3
DQ
Logic D Q
Array D Q
DQ
A4 A5 A6 A7
Output Routing Pool (ORP)
Input Bus
B2
B1
B0
Description
0139A/2064V
The ispLSI 2064VE is a High Density Programmable
Logic Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064VE features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP) and is 100% IEEE 1149.1 Boundary
Scan Testable. The ispLSI 2064VE offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2064ve_06
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Specifications ispLSI 2064VE
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 3
COND.
#
DESCRIPTION1
-280
-200
UNITS
MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass
— 3.5 — 4.5 ns
tpd2
A 2 Data Propagation Delay
— — — 7.0 ns
fmax
A 3 Clock Frequency with Internal Feedback 2
280 — 200 — MHz
fmax (Ext.)
fmax (Tog.)
—
4
Clock
Frequency
with
External
Feedback
(
1
tsu2 +
)tco1
— 5 Clock Frequency, Max. Toggle
— — 133 — MHz
— — 200 — MHz
tsu1
— 6 GLB Reg. Setup Time before Clock, 4 PT Bypass
— — 3.0 — ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
— — — 3.5 ns
th1 — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
— — 0.0 — ns
tsu2
— 9 GLB Reg. Setup Time before Clock
— — 4.0 — ns
tco2
A 10 GLB Reg. Clock to Output Delay
— — — 4.5 ns
th2 — 11 GLB Reg. Hold Time after Clock
— — 0.0 — ns
tr1 A 12 Ext. Reset Pin to Output Delay
— — — 6.0 ns
trw1
— 13 Ext. Reset Pulse Duration
— — 4.0 — ns
tptoeen
B 14 Input to Output Enable
— — — 8.0 ns
tptoedis
C 15 Input to Output Disable
— — — 8.0 ns
tgoeen
B 16 Global OE Output Enable
— — — 5.0 ns
tgoedis
C 17 Global OE Output Disable
— — — 5.0 ns
twh — 18 External Synchronous Clock Pulse Duration, High
— — 2.5 — ns
twl — 19 External Synchronous Clock Pulse Duration, Low
— — 2.5 — ns
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030A/2064VE
5
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