PDF ispLSI2064VE-100LJ44 Data sheet ( Hoja de datos )

Número de pieza	ispLSI2064VE-100LJ44
Descripción	3.3V In-System Programmable High Density SuperFAST PLD
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispLSI® 2064VE 3.3V In-System Programmable High Density SuperFAST™ PLD Features • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 and 32 I/O Pin Versions, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2064V Devices • 3.3V LOW VOLTAGE 2064 ARCHITECTURE — Interfaces with Standard 5V TTL Devices • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 280MHz* Maximum Operating Frequency — tpd = 3.5ns* Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — 3.3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms *Advanced Information Functional Block Diagram Input Bus Output Routing Pool (ORP) B7 B6 B5 B4 A0 Global Routing Pool (GRP) B3 A1 A2 GLB A3 DQ Logic D Q Array D Q DQ A4 A5 A6 A7 Output Routing Pool (ORP) Input Bus B2 B1 B0 Description 0139A/2064V The ispLSI 2064VE is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064VE features in-system programmability through the Boundary Scan Test Ac- cess Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2064VE offers non-volatile reprogrammability of the logic, as well as the intercon- nect, to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2064VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com September 2000 2064ve_06 1 1 page Specifications ispLSI 2064VE External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 3 COND. # DESCRIPTION1 -280 -200 UNITS MIN. MAX. MIN. MAX. tpd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 3.5 — 4.5 ns tpd2 A 2 Data Propagation Delay — — — 7.0 ns fmax A 3 Clock Frequency with Internal Feedback 2 280 — 200 — MHz fmax (Ext.) fmax (Tog.) — 4 Clock Frequency with External Feedback ( 1 tsu2 + )tco1 — 5 Clock Frequency, Max. Toggle — — 133 — MHz — — 200 — MHz tsu1 — 6 GLB Reg. Setup Time before Clock, 4 PT Bypass — — 3.0 — ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass — — — 3.5 ns th1 — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass — — 0.0 — ns tsu2 — 9 GLB Reg. Setup Time before Clock — — 4.0 — ns tco2 A 10 GLB Reg. Clock to Output Delay — — — 4.5 ns th2 — 11 GLB Reg. Hold Time after Clock — — 0.0 — ns tr1 A 12 Ext. Reset Pin to Output Delay — — — 6.0 ns trw1 — 13 Ext. Reset Pulse Duration — — 4.0 — ns tptoeen B 14 Input to Output Enable — — — 8.0 ns tptoedis C 15 Input to Output Disable — — — 8.0 ns tgoeen B 16 Global OE Output Enable — — — 5.0 ns tgoedis C 17 Global OE Output Disable — — — 5.0 ns twh — 18 External Synchronous Clock Pulse Duration, High — — 2.5 — ns twl — 19 External Synchronous Clock Pulse Duration, Low — — 2.5 — ns 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Table 2-0030A/2064VE 5 5 Page 64-I/O Signal Locations Signal RESET GOE 0, GOE 1 Y0, Y1, Y2 BSCAN TDI/IN 0 TCK/IN 3 TMS/IN 1 TDO/IN 2 GND 100-Ball caBGA 100-Pin TQFP D2 11 F9, E1 62, 13 E3, F6, F8 10, 65, 60 E5 15 F2 16 G10 59 J5 37 B6 87 B7, F1, G9, K6 14, 39, 61, 86 VCC A5, E2, F10, J4 12, 36, 63, 89 NC1 A6, A8, C3, C4, 4, 9, 21, 25, D1, D6, D8, E7, 31, 38, 44, 50, E9, E10, F4, 54, 64, 66, 71, G3, G5, H7, H8, 75, 81, 88, 94, K3, K5 100 1. NC pins are not to be connected to any active signals, VCC or GND. 32-I/O Signal Locations Signal GOE 0/ IN 3 GOE 1/Y0 RESET/Y1 BSCAN TDI/IN 0 TMS/IN 2 TDO/IN 1 TCK/Y2 GND VCC NC1 44-Pin TQFP 40 5 29 7 8 30 18 27 17, 39 6, 28 — 44-Pin PLCC 2 11 35 13 14 36 24 33 1, 23 12, 34 — 1. NC pins are not to be connected to any active signals, VCC or GND. Specifications ispLSI 2064VE I/O Locations 100 Signal caBGA I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 G1 F3 E4 H1 G2 J1 H2 K1 J2 K2 H3 J3 G4 H4 K4 H5 F5 J6 K7 H6 K8 G6 J7 K9 J8 K10 J9 J10 H9 H10 G7 G8 D10 E8 F7 C10 D9 B10 C9 A10 B9 A9 C8 B8 D7 C7 A7 C6 E6 B5 A4 C5 A3 D5 B4 A2 B3 A1 B2 B1 C2 C1 D4 D3 100 TQFP 17 18 19 20 22 23 24 26 27 28 29 30 32 33 34 35 40 41 42 43 45 46 47 48 49 51 52 53 55 56 57 58 67 68 69 70 72 73 74 76 77 78 79 80 82 83 84 85 90 91 92 93 95 96 97 98 99 1 2 3 5 6 7 8 44 TQFP 9 10 11 12 13 14 15 16 19 20 21 22 23 24 25 26 31 32 33 34 35 36 37 38 41 42 43 44 1 2 3 4 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 44 PLCC 15 16 17 18 19 20 21 22 25 26 27 28 29 30 31 32 37 38 39 40 41 42 43 44 3 4 5 6 7 8 9 10 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 11 11 Page

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