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ispLSI2064E-200LT100 の電気的特性と機能

ispLSI2064E-200LT100のメーカーはLattice Semiconductorです、この部品の機能は「In-System Programmable SuperFAST High Density PLD」です。


製品の詳細 ( Datasheet PDF )

部品番号 ispLSI2064E-200LT100
部品説明 In-System Programmable SuperFAST High Density PLD
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ispLSI2064E-200LT100 Datasheet, ispLSI2064E-200LT100 PDF,ピン配置, 機能
ispLSI® 2064E
In-System Programmable
SuperFAST™ High Density PLD
Features
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functionally and JEDEC Upward Compatible
with ispLSI 2064 Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 200 MHz Maximum Operating Frequency
tpd = 4.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O Supports Mixed
Voltage Systems
— PCI Compatible Outputs
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Input Bus
Output Routing Pool (ORP)
B7 B6 B5 B4
A0
Global Routing Pool
(GRP)
B3
A1
A2 GLB
A3
DQ
Logic D Q
Array D Q
DQ
A4 A5 A6 A7
Output Routing Pool (ORP)
Input Bus
B2
B1
B0
Description
0139/2064E
The ispLSI 2064E is a High Density Programmable Logic
Device. The device contains 64 Registers, 64 Universal
I/O pins, four Dedicated Input Pins, three Dedicated
Clock Input Pins, two dedicated Global OE input pins and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2064E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2064E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2064E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
2064e_05
1

1 Page





ispLSI2064E-200LT100 pdf, ピン配列
Specifications ispLSI 2064E
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................................... -0.5 to +7.0V
Input Voltage Applied .............................. -2.5 to VCC +1.0V
Off-State Output Voltage Applied ........... -2.5 to VCC +1.0V
Storage Temperature ..................................... -65 to 150°C
Case Temp. with Power Applied .................... -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ............ 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
VCC
VCCIO
VIL
VIH
PARAMETER
Supply Voltage: Logic Core, Input Buffers
5V
Supply Voltage: Output Drivers
3.3V
Input Low Voltage
Input High Voltage
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
C1
C2
C3
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
Clock Capacitance
TA = 0°C to +70°C
MIN.
4.75
4.75
3.0
0
2.0
MAX. UNITS
5.25 V
5.25 V
3.6 V
0.8 V
Vcc+1
V
Table 2-0005/2096E
TYPICAL
8
8
10
UNITS
pf
pf
pf
TEST CONDITIONS
VCC = 5.0V, VIN = 2.0V
VCC = 5.0V, VI/O = 2.0V
VCC = 5.0V, VY = 2.0V
Table 2-0006/2064e
Erase/Reprogram Specification
PARAMETER
Erase/Reprogram Cycles
MINIMUM
10,000
MAXIMUM
UNITS
Cycles
Table 2-0008/2064e
3


3Pages


ispLSI2064E-200LT100 電子部品, 半導体
Specifications ispLSI 2064E
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER #2
DESCRIPTION
Inputs
tio 20 Input Buffer Delay
tdin 21 Dedicated Input Delay
GRP
tgrp 22 GRP Delay
GLB
t4ptbpc
t4ptbpr
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
t1ptxor
t20ptxor
txoradj
tgbp
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay 3
28 GLB Register Bypass Delay
tgsu
tgh
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
tgco
31 GLB Register Clock to Output Delay
tgro
tptre
tptoe
tptck
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
ORP
torp
torpbp
36 ORP Delay
37 ORP Bypass Delay
Outputs
tob
tsl
toen
todis
tgoe
38 Output Buffer Delay
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
Clocks
tgy0
tgy1/2
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
Global Reset
tgr 45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
-200
-135
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
0.5
1.1
0.5 0.5
1.7 2.2
ns
ns
0.6 1.2 1.7 ns
1.4
1.9
2.9
2.9
2.9
0.5
1.2
2.3
0.3
0.6
4.3
4.9
1.0 4.0
3.7 5.8
4.2 5.8
5.2 6.8
5.2 7.3
5.2 8.0
0.5 0.5
0.7 1.2
4.3 4.0
0.3 0.3
1.1 1.3
6.0 6.1
6.9 8.6
2.5 5.5 4.1 7.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.9
0.4
1.0 1.4
0.5 0.4
ns
ns
1.6
1.5
2.0
2.0
2.0
1.6 1.6
1.5 1.0
3.4 4.2
3.4 4.2
3.6 4.8
ns
ns
ns
ns
ns
0.7 0.7 1.6 1.6 2.7 2.7
0.9 0.9 1.8 1.8 2.7 2.7
ns
ns
3.4
6.3 9.2 ns
Table 2-0036A/2064E
6

6 Page



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部品番号部品説明メーカ
ispLSI2064E-200LT100

In-System Programmable SuperFAST High Density PLD

Lattice Semiconductor
Lattice Semiconductor


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