PDF ispLSI2032VL-180LT48 Data sheet ( Hoja de datos )

Número de pieza	ispLSI2032VL-180LT48
Descripción	2.5V In-System Programmable SuperFAST High Density PLD
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispLSI® 2032VL 2.5V In-System Programmable SuperFAST™ High Density PLD Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — 32 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2032V and 2032VE Devices • 2.5V LOW VOLTAGE 2032 ARCHITECTURE — Interfaces With Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant) — 45 mA Typical Active Current • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 180 MHz Maximum Operating Frequency — tpd = 5.0 ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — 2.5V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram A0 Global Routing Pool (GRP) A1 A2 GLB A3 DQ Logic D Q Array D Q DQ A7 A6 A5 A4 Description 0139Bisp/2000 The ispLSI 2032VL is a High Density Programmable Logic Device containing 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032VL features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2032VL offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2032VL device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. A7 (see Figure 1). There are a total of eight GLBs in the ispLSI 2032VL device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com September 2000 2032vl_02 1 1 page Specifications ispLSI 2032VL External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 3 COND. # DESCRIPTION1 -180 -135 -110 UNITS MIN. MAX. MIN. MAX. MIN. MAX. tpd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 5.0 — 7.5 — 10.0 ns tpd2 A 2 Data Propagation Delay — 7.5 — 10.0 — 13.0 ns fmax A 3 Clock Frequency with Internal Feedback 2 180 — 135 — 110 — MHz fmax (Ext.) fmax (Tog.) — 4 Clock Frequency with External Feedback (1 tsu2 + )tco1 118 — 100 — 80.0 — MHz — 5 Clock Frequency, Max. Toggle 200 — 167 — 125 — MHz tsu1 — 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 3.0 — 4.0 — 5.5 — ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass — 4.0 — 4.5 — 5.0 ns th1 — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 — 0.0 — 0.0 — ns tsu2 — 9 GLB Reg. Setup Time before Clock 4.5 — 5.5 — 7.5 — ns tco2 A 10 GLB Reg. Clock to Output Delay — 5.0 — 5.5 — 6.0 ns th2 — 11 GLB Reg. Hold Time after Clock 0.0 — 0.0 — 0.0 — ns tr1 A 12 Ext. Reset Pin to Output Delay, ORP Bypass — 6.0 — 8.0 — 12.5 ns trw1 — 13 Ext. Reset Pulse Duration 4.0 — 5.0 — 6.5 — ns tptoeen B 14 Input to Output Enable — 10.0 — 12.0 — 14.5 ns tptoedis C 15 Input to Output Disable — 10.0 — 12.0 — 14.5 ns tgoeen B 16 Global OE Output Enable — 5.0 — 6.0 — 7.0 ns tgoedis C 17 Global OE Output Disable — 5.0 — 6.0 — 7.0 ns twh — 18 External Synchronous Clock Pulse Duration, High 2.5 — 3.0 — 4.0 — ns twl — 19 External Synchronous Clock Pulse Duration, Low 2.5 — 3.0 — 4.0 — ns 1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Table 2-0030B/2032VL 5 5 Page Pin Configuration ispLSI 2032VL 48-Pin TQFP Pinout Diagram Specifications ispLSI 2032VL I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC BSCAN 1TDI/IN 0 I/O 0 I/O 1 I/O 2 2NC 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 ispLSI 2032VL 31 7 Top View 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 NC2 I/O 18 I/O 17 I/O 16 TMS/NC2 RESET/Y11 VCC TCK/Y21 I/O 15 I/O 14 I/O 13 I/O 12 48TQFP/2032VL 1. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, VCC or GND. Signal Configuration ispLSI 2032VL 49-Ball caBGA Signal Diagram 7654321 A ANC1 I/O 21 I/O GOE I/O 23 0 25 I/O NC1 27 B BI/O I/O I/O I/O I/O I/O I/O 18 17 20 22 24 26 30 C CI/O 16 TMS/ NC1 I/O 19 GND I/O 28 I/O 29 Y0 D DRESET/ Y1 I/O 15 VCC NC1 VCC I/O 31 BSCAN E TCK/ Y2 I/O 13 I/O 12 GND I/O 3 TDI/ I/O IN0 0 E F FI/O I/O I/O I/O I/O I/O I/O 14 10 8 6 4 1 2 G GNC1 I/O 11 I/O TDO/ I/O 9 IN1 7 I/O NC1 5 ispLSI 2032VL Bottom View 7 6 5 4 3 2 1 49-BGA/2032VL 1. NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. 11 11 Page

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