PDF ispLSI2032VL-135LT44I Data sheet ( Hoja de datos )

Número de pieza	ispLSI2032VL-135LT44I
Descripción	2.5V In-System Programmable SuperFAST High Density PLD
Fabricantes	Lattice Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de ispLSI2032VL-135LT44I (archivo pdf) en la parte inferior de esta página. Total 11 Páginas
No Preview Available ! ispLSI® 2096VL 2.5V In-System Programmable SuperFAST™ High Density PLD Features Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2096V and 2096VE Devices • 2.5V LOW VOLTAGE 2096 ARCHITECTURE — Interfaces with Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant) — 85 mA Typical Active Current • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 165 MHz Maximum Operating Frequency — tpd = 5.5 ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — 2.5V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Output Routing Pool (ORP) C7 C6 C5 C4 A0 DQ A1 Logic D Q A2 GLB Array D Q DQ A3 A4 A5 A6 A7 Output Routing Pool (ORP) Output Routing Pool (ORP) C3 C2 C1 C0 B7 Global Routing Pool (GRP) B6 B5 B4 B0 B1 B2 B3 Output Routing Pool (ORP) Description 0919/2096VL The ispLSI 2096VL is a High Density Programmable Logic Device containing 96 Registers, six Dedicated Input pins, three Dedicated Clock Input pins, two dedi- cated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096VL fea- tures in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2096VL offers non- volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2096VL device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. C7 (see Figure 1). There are a total of 24 GLBs in the ispLSI 2096VL device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The devices also have 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control, and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com September 2000 2096vl_02 1 1 page Specifications ispLSI 2096VL External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 3 COND. # DESCRIPTION1 -165 -135 -100 UNITS MIN. MAX. MIN. MAX. MIN. MAX. tpd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 5.5 — 7.5 — 10.0 ns tpd2 A 2 Data Propagation Delay — 8.0 — 10.0 — 13.0 ns fmax A 3 Clock Frequency with Internal Feedback 2 165 — 135 — 100 — MHz fmax (Ext.) fmax (Tog.) — 4 Clock Frequency with External Feedback (1 tsu2 + )tco1 118 — 95 — 77 — MHz — 5 Clock Frequency, Max. Toggle 166 — 143 — 100 — MHz tsu1 — 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 3.5 — 5.0 — 6.5 — ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass — 4.0 — 4.5 — 5.0 ns th1 — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 — 0.0 — 0.0 — ns tsu2 — 9 GLB Reg. Setup Time before Clock 4.5 — 6.0 — 8.0 — ns tco2 A 10 GLB Reg. Clock to Output Delay — 5.0 — 5.5 — 6.0 ns th2 — 11 GLB Reg. Hold Time after Clock 0.0 — 0.0 — 0.0 — ns tr1 A 12 Ext. Reset Pin to Output Delay, ORP Bypass — 6.0 — 8.0 — 13.5 ns trw1 — 13 Ext. Reset Pulse Duration 5.0 — 5.5 — 6.5 — ns tptoeen B 14 Input to Output Enable — 10.0 — 12.0 — 15.0 ns tptoedis C 15 Input to Output Disable — 10.0 — 12.0 — 15.0 ns tgoeen B 16 Global OE Output Enable — 6.0 — 7.0 — 9.0 ns tgoedis C 17 Global OE Output Disable — 6.0 — 7.0 — 9.0 ns twh — 18 External Synchronous Clock Pulse Duration, High 3.0 — 3.5 — 5.0 — ns twl — 19 External Synchronous Clock Pulse Duration, Low 3.0 — 3.5 — 5.0 — ns 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Table 2-0030/2096VL 5 5 Page Specifications ispLSI 2096VL Part Number Description Device Family ispLSI 2096VL — XX X XXXX X Device Number Speed 165 = 165 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax ispLSI 2096VL Ordering Information FAMILY ispLSI fmax (MHz) 165 135 100 tpd (ns) 5.5 7.5 10 COMMERCIAL ORDERING NUMBER ispLSI 2096VL-165LT128 ispLSI 2096VL-135LT128 ispLSI 2096VL-100LT128 FAMILY ispLSI fmax (MHz) 135 tpd (ns) 7.5 INDUSTRIAL ORDERING NUMBER ispLSI 2032VL-135LT44I Grade Blank = Commercial I = Industrial Package T128 = 128-Pin TQFP Power L = Low 0212/2096VL PACKAGE 128-Pin TQFP 128-Pin TQFP 128-Pin TQFP Table 2-0041A/2096VL PACKAGE 44-Pin TQFP Table 2-0041A/2032VL 11 11 Page

Páginas	Total 11 Páginas
PDF Descargar	[ Datasheet ispLSI2032VL-135LT44I.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ispLSI2032VL-135LT44	2.5V In-System Programmable SuperFAST High Density PLD	Lattice Semiconductor
ispLSI2032VL-135LT44I	2.5V In-System Programmable SuperFAST High Density PLD	Lattice Semiconductor
ispLSI2032VL-135LT44I	2.5V In-System Programmable SuperFAST High Density PLD	Lattice Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar