PDF ispLSI2032VE-180LJ44 Data sheet ( Hoja de datos )

Número de pieza	ispLSI2032VE-180LJ44
Descripción	3.3V In-System Programmable High Density SuperFAST PLD
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispLSI® 2032VE 3.3V In-System Programmable High Density SuperFAST™ PLD Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — 32 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2032V Devices • 3.3V LOW VOLTAGE 2032 ARCHITECTURE — Interfaces With Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 225 MHz Maximum Operating Frequency — tpd = 4.0 ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — 3.3V In-System Programmability Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram A0 Global Routing Pool (GRP) A1 A2 GLB A3 DQ Logic D Q Array D Q DQ A7 A6 A5 A4 Description 0139Bisp/2000 The ispLSI 2032VE is a High Density Programmable Logic Device that can be used in both 3.3V and 5V systems. The device contains 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2032VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2032VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. A7 (see Figure 1). There are a total of eight GLBs in the ispLSI 2032VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com September 2000 2032ve_07 1 1 page Specifications ispLSI 2032VE External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 3 COND. # DESCRIPTION1 -225 4 -180 UNITS MIN. MAX. MIN. MAX. tpd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 4.0 – 5.0 ns tpd2 A 2 Data Propagation Delay – 6.0 – 7.5 ns fmax A 3 Clock Frequency with Internal Feedback 2 225 – 180 – MHz fmax (Ext.) fmax (Tog.) – 4 Clock Frequency with External Feedback (1 tsu2 + )tco1 – 5 Clock Frequency, Max. Toggle 154 – 125 – 250 – 200 – MHz MHz tsu1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 2.5 – 3.0 – ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 3.0 – 4.0 ns th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – ns tsu2 – 9 GLB Reg. Setup Time before Clock 3.5 – 4.0 – ns tco2 A 10 GLB Reg. Clock to Output Delay – 4.0 – 5.0 ns th2 – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – ns tr1 A 12 Ext. Reset Pin to Output Delay, ORP Bypass – 5.0 – 6.0 ns trw1 – 13 Ext. Reset Pulse Duration 3.5 – 4.0 – ns tptoeen B 14 Input to Output Enable – 7.0 – 10.0 ns tptoedis C 15 Input to Output Disable – 7.0 – 10.0 ns tgoeen B 16 Global OE Output Enable – 3.5 – 5.0 ns tgoedis C 17 Global OE Output Disable – 3.5 – 5.0 ns twh – 18 External Synchronous Clock Pulse Duration, High 2.0 – 2.5 – ns twl – 19 External Synchronous Clock Pulse Duration, Low 2.0 – 2.5 – ns 1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. 4. -225 speed grade supercedes earlier -200. All parameters other than fmax (internal) are the same. Table 2-0030A/2032VE 5 5 Page Specifications ispLSI 2032VE Signal Descriptions Signal Name GOE 0 Y0 RESET/Y1 BSCAN TDI/IN 0 TMS/NC1 TDO/IN 1 TCK/Y2 GND VCC NC1 I/O Description Global Output Enable Pin Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: (1) Dedicated clock input. This clock input is brought into the Clock Deistribution Network and can optionally be routed to any GLB and/or I/O cell on the device. (2) Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Input – Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input – This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load programming data into the device. TDI/IN0 is also used as one of the two control pins for the ISP State Machine. When BSCAN is high, it functions as a dedicated input pin. Input – When in ISP Mode, controls operation of the ISP State Machine. Output/Input – This pin performs two functions. When BSCAN is logic low, it functions as an output pin pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. Input – This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Serial Shift Register. When BSCAN is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network and can optionally be routed to any GLB and/or I/O cell on the device. Ground (GND) Vcc No Connect Input/Output pins – These are the general purpose I/O pins used by the logic array. Signal Locations Signal GOE 0 Y0 RESET/Y1 BSCAN TDI/IN 0 TMS/NC1 TDO/IN 1 TCK/Y2 GND VCC NC1 44-Pin TQFP 40 5 29 7 8 30 18 27 17, 39 6, 28 — 44-Pin PLCC 2 11 35 13 14 36 24 33 1, 23 12, 34 — 48-Pin TQFP 43 5 31 7 8 32 19 29 18, 42 6, 30 12, 24, 36, 48 49-Ball caBGA A4 C1 D7 D1 E2 C6 G4 E7 C4, E4 D3, D5 A1, A7, D4, G1, G7 I/O Locations Signal 44-Pin TQFP 44-Pin PLCC I/O 0 - I/O 6 9, 10, 11, 12, 13, 14, 15 15, 16, 17, 18, 19, 20, 21 I/O 7 - I/O 13 16, 19, 20, 21, 22, 23, 24 22, 25, 26, 27, 28, 29, 30 I/O 14 - I/O 20 25, 26, 31, 32, 33, 34, 35 31, 32, 37, 38, 39, 40, 41 I/O 21 - I/O 27 36, 37, 38, 41, 42, 43, 44 42, 43, 44, 3, 4, 5, 6 I/O 28 - I/O 31 1, 2, 3, 4 7, 8, 9, 10 1. NC pins are not to be connected to any active signals, VCC or GND. 48-Pin TQFP 9, 10, 11, 13, 14, 15, 16 17, 20, 21, 22, 23, 25, 26 27, 28, 33, 34, 35, 37, 38 39, 40, 41, 44, 45, 46, 47 1, 2, 3, 4 49-Ball caBGA E1, F2, F1, E3, F3, G2, F4 G3, F5, G5, F6, G6, E5, E6 F7, D6, C7, B6, B7, C5, B5 A6, B4, A5, B3, A3, B2, A2 C3, C2, B1, D2 11 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ispLSI2032VE-180LJ44	3.3V In-System Programmable High Density SuperFAST PLD	Lattice Semiconductor

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