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IspLSI2032E-180LT44 の電気的特性と機能

IspLSI2032E-180LT44のメーカーはLattice Semiconductorです、この部品の機能は「In-System Programmable SuperFAST High Density PLD」です。


製品の詳細 ( Datasheet PDF )

部品番号 IspLSI2032E-180LT44
部品説明 In-System Programmable SuperFAST High Density PLD
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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IspLSI2032E-180LT44 Datasheet, IspLSI2032E-180LT44 PDF,ピン配置, 機能
ispLSI® 2032E
In-System Programmable
SuperFAST™ High Density PLD
Features
Functional Block Diagram
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functionally and JEDEC Upward Compatible
with ispLSI 2032 Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 225 MHz Maximum Operating Frequency
tpd = 3.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O (48-Pin Package Only)
Supports Mixed Voltage Systems
— PCI Compatible Outputs (48-Pin Package Only)
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
A0
Global Routing Pool
(GRP)
A1
A2 GLB
A3
DQ
Logic D Q
Array D Q
DQ
A7
A6
A5
A4
0139Bisp/2000
Description
The ispLSI 2032E is a High Density Programmable Logic
Device. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2032E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2032E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
June 1999
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2032e_03
1

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IspLSI2032E-180LT44 pdf, ピン配列
Specifications ispLSI 2032E
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
VCC
VCCIO1
Supply Voltage: Logic Core, Input Buffers
5V
Supply Voltage: Output Drivers
3.3V
VIL Input Low Voltage
VIH Input High Voltage
1. 3.3V I/O operation not available for 44-pin packages.
TA = 0°C to +70°C
MIN.
4.75
4.75
3.0
0
2.0
MAX. UNITS
5.25 V
5.25 V
3.6 V
0.8 V
Vcc+1
V
Table 2-0005/2032E
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
C1
C2
C3
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
Clock Capacitance
Erase/Reprogram Specification
PARAMETER
Erase/Reprogram Cycles
MINIMUM
10,000
TYP
6
7
10
UNITS
pf
pf
pf
TEST CONDITIONS
VCC = 5.0V, VIN = 2.0V
VCC = 5.0V, VI/O = 2.0V
VCC = 5.0V, VY = 2.0V
Table 2-0006/2032E
MAXIMUM
UNITS
Cycles
Table 2-0008/2032E
3


3Pages


IspLSI2032E-180LT44 電子部品, 半導体
Specifications ispLSI 2032E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
COND.4
#2
DESCRIPTION1
-135
-110
UNITS
MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass
7.5 10.0 ns
tpd2
A 2 Data Propagation Delay
10.0 13.0 ns
fmax
A 3 Clock Frequency with Internal Feedback3
137 111 MHz
fmax (Ext.)
fmax (Tog.)
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
)tco1
5 Clock Frequency, Max. Toggle
100 77.0
167 125
MHz
MHz
tsu1
6 GLB Register Setup Time before Clock, 4 PT Bypass
4.0 5.5
ns
tco1
A 7 GLB Register Clock to Output Delay, ORP Bypass
4.5 5.5 ns
th1
8 GLB Register Hold Time after Clock, 4 PT Bypass
0.0 0.0
ns
tsu2
9 GLB Register Setup Time before Clock
5.5 7.5
ns
tco2
10 GLB Register Clock to Output Delay
5.5 6.5 ns
th2 11 GLB Register Hold Time after Clock
0.0 0.0
ns
tr1
A 12 External Reset Pin to Output Delay, ORP Bypass
9.0 12.5 ns
trw1
13 External Reset Pulse Duration
5.0 6.5
ns
tptoeen
B 14 Input to Output Enable
12.0 14.5 ns
tptoedis
C 15 Input to Output Disable
12.0 14.5 ns
tgoeen
B 16 Global OE Output Enable
6.0 7.0 ns
tgoedis
C 17 Global OE Output Disable
6.0 7.0 ns
twh
18 External Synchronous Clock Pulse Duration, High
3.0 4.0
ns
twl
19 External Synchronous Clock Pulse Duration, Low
3.0 4.0
ns
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B/2032E
6

6 Page



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部品番号部品説明メーカ
ispLSI2032E-180LT44

In-System Programmable SuperFAST High Density PLD

Lattice Semiconductor
Lattice Semiconductor
ISPLSI2032E-180LT44

In-System Programmable SuperFAST High Density PLD

Lattice Semiconductor
Lattice Semiconductor
IspLSI2032E-180LT44

In-System Programmable SuperFAST High Density PLD

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ispLSI2032E-180LT48

In-System Programmable SuperFAST High Density PLD

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