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ispLSI1048EA-100LQ128のメーカーはLattice Semiconductorです、この部品の機能は「In-System Programmable High Density PLD」です。 |
部品番号 | ispLSI1048EA-100LQ128 |
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部品説明 | In-System Programmable High Density PLD | ||
メーカ | Lattice Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとispLSI1048EA-100LQ128ダウンロード(pdfファイル)リンクがあります。 Total 14 pages
ispLSI® 1048EA
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Eight Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally Compatible with ispLSI 1048C and 1048E
• NEW FEATURES
— 100% IEEE 1149.1 Boundary Scan Testable
— ispJTAG™ In-System Programmable Via IEEE 1149.1
(JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O supports Mixed
Voltage Systems (VCCIO Pin)
— Open Drain Output Option
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 170 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
Output Routing Pool
E7 E6 E5 E4 E3 E2 E1 E0
A0
A1
A2
A3
Global Routing Pool (GRP)
A4
A5
A6
A7
DQ
DQ
Logic
Array D Q GLB
DQ
D7
D6
D5
D4
D3
D2
D1
D0
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
C0 C1 C2 C3 C4 C5 C6 C7
CLK
Output Routing Pool
0139A/1048EA
Description
The ispLSI 1048EA is a High Density Programmable
Logic Device containing 288 Registers, 96 Universal I/O
pins, eight Dedicated Input pins, four Dedicated Clock
Input pins, two dedicated Global OE input pins, and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 1048EA features 5V in-system programmability
and in-system diagnostic capabilities via IEEE 1149.1
Test Access Port. The ispLSI 1048EA offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect to provide truly reconfigurable systems. A functional
superset of the ispLSI 1048 architecture, the ispLSI
1048EA device adds user selectable 3.3V or 5V I/O and
open-drain output options.
The basic unit of logic on the ispLSI 1048EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinato-
rial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
1048ea_03
1
1 Page Specifications ispLSI 1048EA
Boundary Scan
Figure 2. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
TCK
Tbtch
Tbtsu
Tbtcl
Tbth
Tbtcp
TDO
Data to be
captured
Data to be
driven out
Tbtvo
Tbtco
Valid Data
Tbtcpsu
Tbtcph
Data Captured
Tbtuov
Tbtuco
Valid Data
Tbtoz
Valid Data
Tbtuoz
Valid Data
Symbol
tbtcp
tbtch
tbtcl
tbtsu
tbth
trf
tbtco
tbtoz
tbtvo
tbtcpsu
tbtcph
tbtuco
tbtuoz
tbtuov
Parameter
TCK [BSCAN test] clock pulse width
TCK [BSCAN test] pulse width high
TCK [BSCAN test] pulse width low
TCK [BSCAN test] setup time
TCK [BSCAN test] hold time
TCK [BSCAN test] rise and fall time
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to data output disable
TAP controller falling edge of clock to data output enable
BSCAN test Capture register setup time
BSCAN test Capture register hold time
BSCAN test Update reg, falling edge of clock to valid output
BSCAN test Update reg, falling edge of clock to output disable
BSCAN test Update reg, falling edge of clock to output enable
Min Max Units
100 –
ns
50 – ns
50 – ns
20 – ns
25 – ns
50 – mV/ns
– 25 ns
– 25 ns
– 25 ns
40 – ns
25 – ns
– 50 ns
– 50 ns
– 50 ns
3
3Pages Specifications ispLSI 1048EA
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 4 #2
COND.
DESCRIPTION1
-170
-125
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
A
A
A
—
—
—
1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 5.0 — 7.5 — 10.0 ns
2 Data Propagation Delay, Worst Case Path
— 7.0 — 10.0 — 12.5 ns
3 Clock Frequency with Internal Feedback 3
170 — 125 — 100 — MHz
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
)tco1
125
— 100
— 77
— MHz
5
Clock
Frequency,
Max.
Toggle
(
1
twh +
twl
)
222 — 167 — 125 — MHz
6 GLB Reg. Setup Time before Clock,4 PT Bypass 3.5 — 4.5 — 6.0 — ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
— 3.5 — 4.5 — 6.0 ns
th1
— 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 — 0.0 — 0.0 — ns
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
— 9 GLB Reg. Setup Time before Clock
4.5 — 5.5 — 7.0 — ns
— 10 GLB Reg. Clock to Output Delay
— 4.5 — 5.5 — 7.0 ns
— 11 GLB Reg. Hold Time after Clock
0.0 — 0.0 — 0.0 — ns
A 12 Ext. Reset Pin to Output Delay
— 7.0 — 10.0 — 13.5 ns
— 13 Ext. Reset Pulse Duration
4.0 — 5.0 — 6.5 — ns
B 14 Input to Output Enable
— 9.0 — 12.0 — 15.0 ns
C 15 Input to Output Disable
— 9.0 — 12.0 — 15.0 ns
B 16 Global OE Output Enable
— 6.5 — 7.0 — 9.0 ns
C 17 Global OE Output Disable
— 6.5 — 7.0 — 9.0 ns
— 18 External Synchronous Clock Pulse Duration, High 2.25 — 3.0 — 4.0 — ns
— 19 External Synchronous Clock Pulse Duration, Low 2.25 — 3.0 — 4.0 — ns
tsu3
— 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0 — 3.0 — 3.5 — ns
th3 — 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0 — 0.0 — 0.0 — ns
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/1048EA
v.2.0
6
6 Page | |||
ページ | 合計 : 14 ページ | ||
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部品番号 | 部品説明 | メーカ |
ispLSI1048EA-100LQ128 | In-System Programmable High Density PLD | Lattice Semiconductor |