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PDF ispLSI1032E-90LT Data sheet ( Hoja de datos )
| Número de pieza | ispLSI1032E-90LT | |
| Descripción | In-System Programmable High Density PLD | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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ispLSI ® 1032E
In-System Programmable High Density PLD
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0 C7
DQ
A1 C6
A2 D Q
Logic
C5
A3 Array D Q GLB C4
A4 C3
A5 D Q C2
A6 C1
A7 Global Routing Pool (GRP) C0
B0 B1 B2 B3 B4 B5 B6 B7
CLK
Output Routing Pool
0139A(A1)-isp
Description
The ispLSI 1032E is a High Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1032E device offers 5V non-vola-
tile in-system programmability of the logic, as well as the
interconnects to provide truly reconfigurable systems. A
functional superset of the ispLSI 1032 architecture, the
ispLSI 1032E device adds two new global output enable
pins.
The basic unit of logic on the ispLSI 1032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 1032E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any GLB on the device.
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
1032e_08
1
1 page  
Specifications ispLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 4 #2
COND.
DESCRIPTION1
-125
-100
UNITS
MIN. MAX. MIN. MAX.
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
A
A
A
–
–
–
1 Data Propagation Delay, 4PT Bypass, ORP Bypass
2 Data Propagation Delay, Worst Case Path
3 Clock Frequency with Internal Feedback 3
4
Clock
Frequency
with
External
Feedback
(
1
tsu2 +
)tco1
5
Clock
Frequency,
Max.
Toggle
(
1
twh +
)tw1
6 GLB Reg. Setup Time before Clock,4 PT Bypass
– 7.5 – 10.0
– 10.0 – 12.5
125 – 100 –
91.0 – 71.0 –
167 – 125 –
5.0 – 7.0 –
ns
ns
MHz
MHz
MHz
ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
– 5.0 – 6.0 ns
th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 – 0.0 –
ns
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
– 9 GLB Reg. Setup Time before Clock
– 10 GLB Reg. Clock to Output Delay
– 11 GLB Reg. Hold Time after Clock
A 12 Ext. Reset Pin to Output Delay
– 13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
C 15 Input to Output Disable
B 16 Global OE Output Enable
C 17 Global OE Output Disable
– 18 External Synchronous Clock Pulse Duration, High
– 19 External Synchronous Clock Pulse Duration, Low
6.0 – 8.0 –
– 6.0 – 7.0
0.0 – 0.0 –
– 10.0 – 13.5
5.0 – 6.5 –
– 12.0 – 15.0
– 12.0 – 15.0
– 7.0 – 9.0
– 7.0 – 9.0
3.0 – 4.0 –
3.0 – 4.0 –
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu3
– 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
3.0 – 3.5 –
ns
th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
0.0 – 0.0 –
ns
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/1032E
5
5 Page 
Specifications ispLSI 1032E
ispLSI 1032E Timing Model
I/O Cell
GRP
Ded. In
I/O Pin
(Input)
#59
#28
I/O Reg Bypass
#22
Input
D Register Q
RST
#23 - 27
Reset
GRP4
#30
GRP Loading
Delay
#29, 31 - 33
GLB
Feedback
#34 Comb 4 PT Bypass
Reg 4 PT Bypass
#35
20 PT
XOR Delays
#36 - 38
#59
GLB Reg Bypass
#39
GLB Reg
Delay
DQ
RST
#40 - 43
ORP
I/O Cell
ORP Bypass
#48
ORP
Delay
#47
#49, 50
I/O Pin
(Output)
#51, 52
Y1,2,3
Clock
Distribution
#55 - 58
Control RE
PTs OE
#44 - 46 CK
Y0
GOE 0,1
#54
#53
Derivations of tsu, th and tco from the Product Term Clock1
tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))
= (#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
2.2 ns = (0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
th = Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
= (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
3.5 ns = (0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
tco = Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#22 + #30 + #46) + (#42) + (#47 + #49)
10.9 ns = (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
Derivations of tsu, th and tco from the Clock GLB 1
tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))
= (#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
2.9 ns = (0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8)
th = Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
= (#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
2.7 ns = (1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
tco = Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#54 + #42 + #56) + (#42) + (#47 + #49)
5.5 ns = (1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
1. Calculations are based upon timing specifications for the ispLSI 1032E-125.
Table 2-0042a/1032E
11
0491
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ispLSI1032E-90LT.PDF ] | |
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