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PDF ISPLSI1032E-90LJ Data sheet ( Hoja de datos )
| Número de pieza | ISPLSI1032E-90LJ | |
| Descripción | High-Density Programmable Logic | |
| Fabricantes | Lattice Semiconductor | |
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ispLSI® 1032
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 90 MHz Maximum Operating Frequency
— fmax = 60 MHz for Industrial and Military/883 Devices
— tpd = 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0 C7
A1 D Q C6
A2 D Q C5
Logic
A3
Array D Q GLB
C4
A4 C3
DQ
A5 C2
A6 C1
A7 Global Routing Pool (GRP) C0
B0 B1 B2 B3 B4 B5 B6 B7
CLK
Output Routing Pool
Description
The ispLSI 1032 is a High-Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1032 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1032 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see figure 1). There are a total of 32 GLBs in the
ispLSI 1032 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
March 1999
1032_07
1
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Specifications ispLSI 1032
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 5
COND.
#2
DESCRIPTION1
-90 -80 -60
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT bypass, ORP bypass – 12 – 15 – 20 ns
tpd2
A 2 Data Propagation Delay, Worst Case Path
– 17 – 20 – 25 ns
fmax (Int.)
A 3 Clock Frequency with Internal Feedback3
90.9 – 80 – 60 – MHz
fmax (Ext.)
–
4
Clock
Frequency
with
External
Feedback(tsu2
1
+
)tco1
58.8 –
50
–
38
– MHz
fmax (Tog.) – 5 Clock Frequency, Max Toggle4
125 – 100 – 83 – MHz
tsu1
– 6 GLB Reg. Setup Time before Clock, 4PT bypass
6 – 7 – 9 – ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP bypass
– 8 – 10 – 13 ns
th1
– 8 GLB Reg. Hold Time after Clock, 4 PT bypass
0 – 0 – 0 – ns
tsu2
– 9 GLB Reg. Setup Time before Clock
9 – 10 – 13 – ns
tco2
– 10 GLB Reg. Clock to Output Delay
– 10 – 12 – 16 ns
th2 – 11 GLB Reg. Hold Time after Clock
0 – 0 – 0 – ns
tr1 A 12 Ext. Reset Pin to Output Delay
– 15 – 17 – 22.5 ns
trw1
– 13 Ext. Reset Pulse Duration
10 – 10 – 13 – ns
ten B 14 Input to Output Enable
– 15 – 18 – 24 ns
tdis C 15 Input to Output Disable
– 15 – 18 – 24 ns
twh – 16 Ext. Sync. Clock Pulse Duration, High
4 – 5 – 6 – ns
twl – 17 Ext. Sync. Clock Pulse Duration, Low
4 – 5 – 6 – ns
tsu5
– 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) 2 – 2 – 2.5 – ns
th5 – 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 6.5 – 6.5 – 8.5 – ns
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions section.
Table 2-0030-32/90,80,60C
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Specifications ispLSI 1032
Pin Description
Name
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
IN 4 - IN 7
TQFP Pin Numbers
17, 18, 19, 20,
21, 22, 23, 28,
29, 30, 31, 32,
33, 34, 35, 36,
40, 41, 42, 43,
44, 45, 46, 47,
48, 53, 54, 55,
56, 57, 58, 59,
67, 68, 69, 70,
71, 72, 73, 78,
79, 80, 81, 82,
83, 84, 85, 86,
90, 91, 92, 93,
94, 95, 96, 97,
98, 3, 4, 5,
6, 7, 8, 9
66, 87, 89, 10
Description
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Dedicated input pins to the device.
ispEN
SDI/IN 01
MODE/IN 11
SDO/IN 21
SCLK/IN 3 1
NC2
14
16
37
39
60
1, 2, 24, 25,
26, 27, 49, 50,
51, 52, 74, 75
76, 77, 99, 100
Input —Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input —This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input —This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output —This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input —This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
No Connect
RESET
Y0
Y1
Y2
Y3
GND
VCC
15
11
65
62
61
13, 38, 63, 88
12, 64
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
Ground (GND)
VCC
1. Pins have dual function capability
2. NC pins are not to be connected to any active signals, Vcc or GND.
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