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ispLSI1032E-70LTI の電気的特性と機能

ispLSI1032E-70LTIのメーカーはLattice Semiconductorです、この部品の機能は「High-Density Programmable Logic」です。


製品の詳細 ( Datasheet PDF )

部品番号 ispLSI1032E-70LTI
部品説明 High-Density Programmable Logic
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ispLSI1032E-70LTI Datasheet, ispLSI1032E-70LTI PDF,ピン配置, 機能
ispLSI® and pLSI® 1032E
High-Density Programmable Logic
Features
• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— In-System Programmable (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispEXPERT™ – LOGIC COMPILER AND COMPLETE
ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS
THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0 C7
DQ
A1 C6
A2 D Q
Logic
C5
A3 Array D Q GLB C4
A4 C3
A5 D Q C2
A6 C1
A7 Global Routing Pool (GRP) C0
B0 B1 B2 B3 B4 B5 B6 B7 CLK
Output Routing Pool
0139A(A1)-isp
Description
The ispLSI and pLSI 1032E are High Density Program-
mable Logic Devices containing 192 Registers, 64
Universal I/O pins, eight Dedicated Input pins, four Dedi-
cated Clock Input pins and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between
all of these elements. The ispLSI 1032E features 5-Volt
in-system programmability and in-system diagnostic ca-
pabilities. The ispLSI 1032E device offers non-volatile
reprogrammability of the logic, as well as the intercon-
nects to provide truly reconfigurable systems. It is
architecturally and parametrically compatible to the pLSI
1032E device, but multiplexes four input pins to control
in-system programming. A functional superset of the
ispLSI and pLSI 1032 architecture, the ispLSI and pLSI
1032E devices add two new global output enable pins.
The basic unit of logic on the ispLSI and pLSI 1032E
devices is the Generic Logic Block (GLB). The GLBs are
labeled A0, A1…D7 (see Figure 1). There are a total of 32
GLBs in the ispLSI and pLSI 1032E devices. Each GLB
has 18 inputs, a programmable AND/OR/Exclusive OR
array, and four outputs which can be configured to be
either combinatorial or registered. Inputs to the GLB
come from the GRP and dedicated inputs. All of the GLB
outputs are brought back into the GRP so that they can
be connected to the inputs of any GLB on the device.
Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
October 1998
1032E_06
1

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ispLSI1032E-70LTI pdf, ピン配列
Specifications ispLSI and pLSI 1032E
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
VCC
VIL
VIH
Supply Voltage
Input Low Voltage
Input High Voltage
PARAMETER
Commercial TA = 0°C to + 70°C
Industrial
TA = -40°C to + 85°C
Capacitance (TA=25oC, f=1.0 MHz)
MIN.
4.75
4.5
0
2.0
MAX. UNITS
5.25
V
5.5 V
0.8 V
Vcc+1
V
Table 2-0005/1032E
SYMBOL
PARAMETER
C1 Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)
C2 Y0 Clock Capacitance
Data Retention Specifications
TYPICAL
8
UNITS
pf
TEST CONDITIONS
VCC = 5.0V, VPIN = 2.0V
15 pf VCC = 5.0V, VPIN = 2.0V
Table 2-0006/1032E
PARAMETER
Data Retention
ispLSI Erase/Reprogram Cycles
pLSI Erase/Reprogram Cycles
MINIMUM
20
10000
100
MAXIMUM
UNITS
Years
Cycles
Cycles
Table 2-0008/1032E
3


3Pages


ispLSI1032E-70LTI 電子部品, 半導体
Specifications ispLSI and pLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 4 #2
COND.
DESCRIPTION1
-90 -80
-70
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
tpd2
fmax (Int.)
fmax (Ext.)
fmax (Tog.)
tsu1
A
A
A
1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 – 12.0 – 15.0 ns
2 Data Propagation Delay, Worst Case Path
– 12.5 – 15.0 – 17.5 ns
3 Clock Frequency with Internal Feedback 3
90.0 – 80.0 – 70.0 –
4
Clock
Frequency
with
External
Feedback
(
1
tsu2 +
)tco1
69.0
– 61.0
56.0
5
Clock
Frequency,
Max.
Toggle
(
1
twh +
)tw1
125 – 111 – 100 –
6 GLB Reg. Setup Time before Clock,4 PT Bypass 7.5 – 8.5 – 9.0 –
MHz
MHz
MHz
ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
– 6.0 – 6.5 – 7.0 ns
th1
– 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 – 0.0 – 0.0 –
ns
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
– 9 GLB Reg. Setup Time before Clock
8.5 – 10.0 – 11.0 –
ns
– 10 GLB Reg. Clock to Output Delay
– 7.0 – 7.5 – 8.0 ns
– 11 GLB Reg. Hold Time after Clock
0.0 – 0.0 – 0.0 –
ns
A 12 Ext. Reset Pin to Output Delay
– 13.5 – 14.0 – 15.0 ns
– 13 Ext. Reset Pulse Duration
6.5 – 8.0 – 10.0 –
ns
B 14 Input to Output Enable
– 15.0 – 16.5 – 18.0 ns
C 15 Input to Output Disable
– 15.0 – 16.5 – 18.0 ns
B 16 Global OE Output Enable
– 9.0 – 10.0 – 12.0 ns
C 17 Global OE Output Disable
– 9.0 – 10.0 – 12.0 ns
– 18 External Synchronous Clock Pulse Duration, High 4.0 – 4.5 – 5.0 –
ns
– 19 External Synchronous Clock Pulse Duration, Low 4.0 – 4.5 – 5.0 –
ns
tsu3
– 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.5 – 3.5 – 4.0 –
ns
th3
– 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0 – 0.0 – 0.0 –
ns
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B/1032E
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
ispLSI1032E-70LT

In-System Programmable High Density PLD

Lattice Semiconductor
Lattice Semiconductor
ispLSI1032E-70LT

High-Density Programmable Logic

Lattice Semiconductor
Lattice Semiconductor
ISPLSI1032E-70LT

High-Density Programmable Logic

Lattice Semiconductor
Lattice Semiconductor
ispLSI1032E-70LTI

High-Density Programmable Logic

Lattice Semiconductor
Lattice Semiconductor


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