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ISPLSI1032E-70LT の電気的特性と機能

ISPLSI1032E-70LTのメーカーはLattice Semiconductorです、この部品の機能は「High-Density Programmable Logic」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISPLSI1032E-70LT
部品説明 High-Density Programmable Logic
メーカ Lattice Semiconductor
ロゴ Lattice Semiconductor ロゴ 




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ISPLSI1032E-70LT Datasheet, ISPLSI1032E-70LT PDF,ピン配置, 機能
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ispLSI® 1032
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 90 MHz Maximum Operating Frequency
fmax = 60 MHz for Industrial and Military/883 Devices
tpd = 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
A0 C7
A1 D Q C6
A2 D Q C5
Logic
A3
Array D Q GLB
C4
A4 C3
DQ
A5 C2
A6 C1
A7 Global Routing Pool (GRP) C0
B0 B1 B2 B3 B4 B5 B6 B7
CLK
Output Routing Pool
Description
The ispLSI 1032 is a High-Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1032 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1032 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see figure 1). There are a total of 32 GLBs in the
ispLSI 1032 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
March 1999
1032_07
1
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ISPLSI1032E-70LT pdf, ピン配列
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Specifications ispLSI 1032
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the Absolute Maximum Ratingsmay cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
VCC
VIL
VIH
PARAMETER
Supply Voltage
Input Low Voltage
Commercial
Industrial
Military/883
TA = 0°C to +70°C
TA = -40°C to +85°C
TC = -55°C to +125°C
Input High Voltage
MIN.
4.75
4.5
4.5
0
2.0
Capacitance (TA=25oC, f=1.0 MHz)
MAX.
UNITS
5.25
5.5 V
5.5
0.8 V
Vcc + 1
V
Table 2- 0005Aisp w/mil.eps
SYMBOL PARAMETER
C1 Dedicated Input Capacitance
C2 I/O and Clock Capacitance
1. Guaranteed but not 100% tested.
Commercial/Industrial
Military
MAXIMUM1
8
10
10
Data Retention Specifications
UNITS
pf
pf
pf
TEST CONDITIONS
VCC=5.0V, VIN=2.0V
VCC=5.0V, VIN=2.0V
VCC=5.0V, VI/O, VY=2.0V
Table 2- 0006
PARAMETER
Data Retention
Erase/Reprogram Cycles
MINIMUM
20
10000
MAXIMUM
UNITS
Years
Cycles
Table 2- 0008B
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ISPLSI1032E-70LT 電子部品, 半導体
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Specifications ispLSI 1032
Internal Timing Parameters1
PARAMETER #2 DESCRIPTION
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
20 I/O Register Bypass
21 I/O Latch Delay
22 I/O Register Setup Time before Clock
23 I/O Register Hold Time after Clock
24 I/O Register Clock to Out Delay
25 I/O Register Reset to Out Delay
26 Dedicated Input Delay
GRP
tgrp1
tgrp4
tgrp8
tgrp12
tgrp16
tgrp32
27 GRP Delay, 1 GLB Load
28 GRP Delay, 4 GLB Loads
29 GRP Delay, 8 GLB Loads
30 GRP Delay, 12 GLB Loads
31 GRP Delay, 16 GLB Loads
32 GRP Delay, 32 GLB Loads
GLB
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgr
tptre
tptoe
tptck
33 4 Product Term Bypass Path Delay
34 1 Product Term/XOR Path Delay
35 20 Product Term/XOR Path Delay
36 XOR Adjacent Path Delay3
37 GLB Register Bypass Delay
38 GLB Register Setup Time before Clock
39 GLB Register Hold Time after Clock
40 GLB Register Clock to Output Delay
41 GLB Register Reset to Output Delay
42 GLB Product Term Reset to Register Delay
43 GLB Product Term Output Enable to I/O Cell Delay
44 GLB Product Term Clock Delay
ORP
torp
torpbp
45 ORP Delay
46 ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
-90 -80 -60
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
1.6 2.0 2.7
2.4 3.0 4.0
4.8 5.5 7.3
2.1 1.0 1.3
2.4 3.0 4.0
2.8 2.5 3.3
3.2 4.0 5.3
ns
ns
ns
ns
ns
ns
ns
1.2 1.5 2.0 ns
1.6 2.0 2.7 ns
2.4 3.0 4.0 ns
3.0 3.8 5.0 ns
3.6 4.5 6.0 ns
6.4 8.0 10.6 ns
5.2 6.5 8.6 ns
5.7 7.0 9.3 ns
7.0 8.0 10.6 ns
8.2 9.5 12.7 ns
0.8 1.0 1.3 ns
1.2 1.0 1.3 ns
3.6 4.5 6.0 ns
1.6 2.0 2.7 ns
2.0 2.5 3.3 ns
8.0 10.0 13.3 ns
7.8 9.0 12.0 ns
2.8 6.0 3.5 7.5 4.6 9.9 ns
2.4 2.5 3.3 ns
0.4 0.5 0.7 ns
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共有リンク

Link :


部品番号部品説明メーカ
ispLSI1032E-70LJ

In-System Programmable High Density PLD

Lattice Semiconductor
Lattice Semiconductor
ispLSI1032E-70LJ

High-Density Programmable Logic

Lattice Semiconductor
Lattice Semiconductor
ISPLSI1032E-70LJ

High-Density Programmable Logic

Lattice Semiconductor
Lattice Semiconductor
ispLSI1032E-70LJI

High-Density Programmable Logic

Lattice Semiconductor
Lattice Semiconductor


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